EP80579 Datasheet, PDF (1013/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
26.3.2.4
Offset 2Ch: FRINDEX - Frame Index Register
This register is used by the host controller to index into the periodic frame list. The
register updates every 125 microseconds (once each microframe). Bits [12:3] are used
to select a particular entry in the Periodic Frame List during periodic schedule
execution. The number of bits used for the index is fixed at 10 since only 1024-entry
frame lists are supported. This register must be written as a DWord. Word and byte
writes produce undefined results. This register cannot be written unless the Host
Controller is in the Halted state as indicated by the HCHalted bit (USB 2.0STS register).
A write to this register while the Run/Stop bit is set to a one (USB 2.0CMD register)
produces undefined results. Writes to this register also affect the SOF value. See
Section 4 of the EHCI Specification for details.
Table 26-43. Offset 2Ch: FRINDEX - Frame Index Register
Description:
View: PCI
BAR: MBAR
Bus:Device:Function: 0:29:7
Offset Start: 2Ch
Offset End: 2Fh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 :14
13 :00
Bit Acronym
Bit Description
Sticky
Reserved
FLCI
Reserved.
Frame List Current Index/Frame Number: The value
in this register increments at the end of each time frame
(e.g., microframe).Bits [12:3] are used for the Frame List
current index. This means that each location of the frame
list is accessed eight times (frames or microframes)
before moving to the next index.
Bit Reset
Value
0h
0h
Bit Access
RW
26.3.2.5
The SOF frame number value for the bus SOF token is derived or alternatively managed
from this register. Please refer to Section 4 of the EHCI Specification for a detailed
explanation of the SOF value management requirements on the host controller. The
value of FRINDEX must be 125 μs (1 microframe) ahead of the SOF token value. The
SOF value may be implemented as an 11-bit shadow register. For this discussion, this
shadow register is 11 bits and is named SOFV. SOFV updates every 8 microframes. (1
ms). An example implementation to achieve this behavior is to increment SOFV each
time the FRINDEX[2:0] increments from a zero to a one.
Software must use the value of FRINDEX to derive the current microframe number and
to provide the get microframe number function required for client drivers. Therefore,
the value of FRINDEX and the value of SOFV must be kept consistent if chip is reset or
software writes to FRINDEX. Writes to FRINDEX must also write-through
FRINDEX[13:3] to SOFV[10:0]. In order to keep the update as simple as possible,
software must never write a FRINDEX value where the three least significant bits are
111b or 000b.
Offset 30h: CTRLDSSEGMENT - Control Data Structure
Segment Register
This 32-bit register corresponds to the most significant address bits [63:32] for all
EHCI data structures. Since the 64-bit Addressing Capability field is hardwired in
HCCPARAMS to one, then this register is used with the link pointers to construct 64-bit
addresses to EHCI control data structures. This register is concatenated with the link
pointer from either the PERIODICLISTBASE, ASYNCLISTADDR, or any control data
structure link field to construct a 64-bit address. This register allows the host software
to locate all control data structures within the same 4 GByte memory segment.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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