EP80579 Datasheet, PDF (1187/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 33-20. Offset 05h: LSR - Line Status Register (Sheet 2 of 3)
Description:
View: IA F
Base Address: Base (IO)
Offset Start: 05h
Offset End: 05h
Size: 8 bit
Default: 60h
Power Well: Core
Bit Range
04
03
02
Bit Acronym
Bit Description
Sticky
Break Interrupt: BI is set to a logic 1 when the
received data input is held in the spacing (logic 0) state
for longer than a full word transmission time (that is,
the total time of Start bit + data bits + parity bit + stop
bits).The BI is reset to a logic “0” when the processor
reads the Line Status register.
BI
0 = No Break signal has been received.
1 = Break signal occurred.
In FIFO mode, only one character (equal to 00H), is
loaded into the FIFO regardless of the length of the
break condition. BI shows the break condition for the
character at the top of the FIFO, not the most recently
received character.
Framing Error: FE indicates that the received character
did not have a valid stop bit.
This bit is reset to a logic “0” when the processor reads
the Line Status Register.
0 = No Framing error.
1 = Invalid stop bit has been detected.
FE is set to a logic 1 when the bit following the last data
bit or parity bit is detected as a logic 0 (spacing level). If
FE
the Line Control register had been set for two stop bit
mode, the receiver does not check for a valid second
stop bit. The FE indicator is reset when the processor
reads the Line Status Register. The UART resynchronizes
after a framing error. To do this it assumes that the
framing error was due to the next start bit, so it
samples this “start” bit twice and then takes in the
“data”.
In FIFO mode FE shows a Framing error for the
character at the top of the FIFO, not for the most
recently received character.
Parity Error: PE indicates that the received data
character does not have the correct even or odd parity,
as selected by the even parity select bit. The PE is set to
logic 1 upon detection of a parity error and is reset to a
logic 0 when the processor reads the Line Status
PE
register.
In FIFO mode, PE shows a parity error for the character
at the top of the FIFO, not the most recently received
character.
0 = No Parity error.
1 = Parity error has occurred.
Bit Reset
Value
0h
0h
0h
Bit Access
RO
RO
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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