EP80579 Datasheet, PDF (1357/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Refer to Table 37-1, “Supported Receive Checksum Capabilities” on page 1363 for a
description of supported packet types for receive checksum off loading. Unsupported
packet types will either have the IXSM bit set, or they will not have the IPCS or TCPCS
bits set. IPv6 packets will not have the IPCS bit set, but may have the TCPCS bit set if
the TCP or UDP packet was recognized by the EP80579’s GbE.
Hardware supplies the PIF field to expedite software processing of packets. Software
must examine any packet with PIF set to determine whether to accept the packet. If
PIF is clear, then the packet is known to be for this station, so software need not look at
the packet contents. Packets passing only the Multicast Vector will have PIF set.
Most error information appears only when the store-bad-packet bit (RCTL.SBP) is set
and a bad packet is received. Refer to Figure 37-8 below for a definition of the possible
errors and their bit positions.
Figure 37-8. Receive Errors (RDESC.ERRORS) Layout
7
6
5
4
3
2
1
0
RXE
IPE
TCPE
CXE
Rsvd Rsvd Rsvd
CE
RXE: RX Data Error
IPE: IPv4 Checksum Error
TCPE: TCP/UDP Checksum Error
CXE: Carrier Extension Error (Reserved)
Rsvd: Reserved
Rsvd: Reserved
Rsvd: Reserved
CE: CRC Error or Alignment Error
Note:
The IP and TCP checksum error bits from Figure 37-8 are valid only when the IPv4 or
TCP/UDP checksum(s) is performed on the received packet as indicated via IPCS and
TCPCS. These, along with the other error bits, are valid only when the EOP and DD bit
are set in the descriptor.
Receive checksum errors have no affect on packet filtering.
If receive checksum off loading is disabled (RXCSUM.IPOFL & RXCSUM.TUOFL), the IPE
and TCPE bits will be 0.
In GMII/MII mode, the RXE bit indicates that a data error occurred during the packet
reception that has been detected by the PHY. This generally corresponds to signal
errors occurring during the packet reception. This bit is valid only when the EOP and DD
bits are set and will not be set in descriptors unless RCTL.SBP (store-bad-packets) is
set.
CRC and alignment errors are indicated via the CE bit. Software may distinguish
between these errors by monitoring the respective statistics registers.
Hardware stores additional information in the receive descriptor for 802.1q packets. If
the packet type is 802.1q (determined when a packet matches VET and RCTL.VME =
1), then the special field records the VLAN information and the four byte VLAN
information is stripped from the packet data storage. Otherwise, the special field
contains 0x0000.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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