EP80579 Datasheet, PDF (661/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.6.1.9
Note:
Offset 20h: NDAR0 - Channel 0 Next Descriptor Address Register
The Next Descriptor Address Register (NDAR) contains the lower 32-bit address of the
next descriptor chain in the local system memory. This register is loaded when the next
descriptor address field of a new chain descriptor is read. Additionally, software writes
this register with the address of the first chain descriptor in local memory. All chain
descriptors are required to be aligned on an eight double-word (32-bit) boundary or the
CMI flags an error.
Software must make sure that the Start bit in the CCR and the Channel Active bit in the
CSR are clear prior to writing to the NDAR. The IMCH prevents writing to this register
when these bits are not clear. Writing zero into the NDAR and NDUAR by software does
not start a DMA transfer.
Table 16-305.Offset 20h: NDAR0 - Channel 0 Next Descriptor Address Register
Description:
View: PCI
BAR: EDMALBAR
Bus:Device:Function: 0:1:0
Offset Start: 20h
Offset End: 23h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 00
Bit Acronym
Bit Description
Sticky
NDLADD
Next Descriptor Lower Address: Lower 32 bits of the
local system memory address of the next chain
descriptor in memory to be read by the channel. The
address must be aligned on an eight DWord (32-bit)
boundary or else the IMCH flags an error. This field can
only be written when the Start bit in the CCR and the
Channel Active bit in the CSR are clear.
Bit Reset
Value
0000000h
Bit Access
RWL
16.6.1.10 Offset 24h: NDUAR0 - Channel 0 Next Descriptor Upper
Address Register
The upper address will not be used in the EP80579, which is limited to 32bit
addressing.
The Next Descriptor Upper Address Register (NDUAR) contains the upper 32-bit
address of the next descriptor chain in the local system memory. This register is loaded
when the next descriptor address field of a new chain descriptor is read. Additionally,
software writes this register with the address of the first chain descriptor in local
memory.
Note:
Software must make sure that the Start bit in the CCR and the Channel Active bit in the
CSR are clear prior to writing to the Next Descriptor Upper Address Register (NDAR).
The IMCH prevents writing to this register when these bits are not clear. Writing zero
into the NDAR and NDUAR by application software does not start a DMA transfer.
Note:
Because the EP80579 supports 32 bit addressing only, this register needs to be set to
“0” at all times.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
661