EP80579 Datasheet, PDF (1588/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
39.6.1.2 Offset 00000004h: Int_Ebl - Interrupt Enable Register
Table 39-7. Offset 00000004h: Int_Ebl - Interrupt Enable Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:4:0
Offset Start: 00000004h
Offset End: 00000007h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:5:0
Offset Start: 00000004h
Offset End: 00000007h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 :13
12
11
10
09
08
07
06
05
04
03
02
01
00
Bit Acronym
Bit Description
Sticky
RSVD
Reserved, these bits are always 0
rx_msg Indicates that a message was received.
tx_msg Indicates that a message was sent.
rx_msg_loss
Is set when a new message arrives but the RxMessage
flag MsgAv is set
bus_off
The CAN has reached the bus off state
crc_err
A CRC error occured while receiving or transmitting data
form_err A form error occured while receiving or transmitting data.
ack_err An acknowledge error occured while transmitting data
stuff_err A stuff error occured while transmitting data
bit_err
A bit error occured while receiving or transmitting data
ovr_load An overload condition has occured
ar_loss
The arbitration was lost while sending a message
RSVD
Reserved
int_ebl
int_ebl, global interrupt enable flag.
0 = All interrupts are disabled
1 = Enabled interrupt sources are available
Bit Reset
Value
0h
0h
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
Bit Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1588
August 2009
Order Number: 320066-003US