EP80579 Datasheet, PDF (891/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
transition to a different interface power management state. The time from the request
written to PxCMD.ICC until the link is active is bounded by the maximum recovery
times from Partial or Slumber as outlined in the Serial ATA 1.0a Specification.
HBA Initiated
The HBA may implement aggressive power management, as indicated in HCAP.SALP.
Aggressive power management allows the HBA to initiate an interface power
management state as soon as there are no commands outstanding to the device. This
enables immediate entry into the low power interface state without waiting for software
in power sensitive systems. The PxCMD.ALPE bit defines whether the feature is enabled
and the PxCMD.ASP field controls whether Partial or Slumber is initiated by the HBA
when enabled.
When PxCMD.ALPE is set to '1', if the HBA recognizes that there are no commands to
process, the HBA shall initiate a transition to Partial or Slumber interface power
management state based upon the setting of PxCMD.ASP. The HBA recognizes no
commands to transmit as either:
• PxSACT is set to 0h, and the HBA updates PxCI from a non-zero value to 0h.
• PxCI is set to 0h, and a Set Device Bits FIS is received that updates PxSACT from a
non-zero value to 0h.
If the PxSACT and PxCI registers are both cleared to 0h, and the interface is in an
active state, the HBA shall not initiate placing the interface into a lower power state,
unless PxCMD.ICC is written with an appropriate value.
Before performing a FIS transmission, the HBA must ensure the link is in the active
state. If the link is in the Partial or Slumber interface power management state, a
COMWAKE must be issued, and the HBA must wait until the link is active before
proceeding with transmission of the FIS.
23.6.4.3.2 Software Requirements and Precedence
Software must check HCAP.SSC (Slumber capable) and HCAP.PSC (Partial capable) to
determine if the HBA supports interface power management transitions as an initiator
or a target. If an interface power management state is not supported, then software
shall not write the PxCMD.ICC field nor set the aggressive power management
capability to initiate a transition to that state. Software must set the PxSCTL.IPM field
to disable transition to any unsupported interface power management state. If
HCAP.SSC or HCAP.PSC is cleared to '0', software should disable device-initiated power
management by issuing the appropriate SET FEATURES command to the device.
HBA initiated interface power management requests are higher priority than software
initiated requests. Thus if the HBA and software request transitions to different states
at the same time, the HBA's request shall take precedence over the software request.
23.6.4.3.3 Device D1, D3 States
The D1 and D3 device states are entered when system software has determined that
no commands will be sent to the device for some time. To enter these states, software
may perform two actions. The first is to issue a command to the device to enter the low
power state (STANDY IMMEDIATE for D1, SLEEP for D3), and the second step is to put
the interface into a Slumber power management state (by setting PxCMD.ICC to 6h).
Note: It is recommended that the device initiate a Slumber power management state
when it receives a command to enter the D1 or D3 state.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
891