EP80579 Datasheet, PDF (1704/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Each specific protocol supported by the expansion has it’s own set of timing parameters
as described by the number cycles required for T1, T2, T3, T4 and T5. The reader is
referred to Section 42.4, “Theory of Operation” for explanation of these parameters.
Additionally, the number of wait states required contributes additional cycles required
for a given transaction and will reduce the bandwidth.
Estimated system latencies expressed in terms of Expansion Bus clock cycles are
shown in Table 42-10.
The estimated bandwidth for a given platform configuration is determined as:
BW (Mbit/s) = TransactionSize * LEB_Freq / TotalLatency
where:
• TransactionSize is size of the transaction expressed in bits
• LEB_Freq is the frequency of the external clock being used to clock the Expansion
bus
• TotalLatency is the sum of:
— SytemLatency + T1 + T2 + T3 + T4 + T5 + Wait States
Note:
The appropriate values for these latencies must be used dependending on whether the
transaction is a read or a write.
Note:
This estimate applies to a single, serialized request at the entry to the AIOC (PCI-to-
PCI Bus M Bridge) onto the expansion bus
Table 42-10. LEB Performance Calculation - Estimated AIOC Latencies
AIOC Internal Bus
(MHz)
400
533
800
LEB
(MHz)
80
80
80
AIOC
Latency
Read
(LEB cycles)
31
24
22
AIOC
Latency
Write
(LEB cycles)
27
21
19
400
66
26
22
533
66
19
17
800
66
17
15
Note:
Note:
Note: The system is assumed to be otherwise quiescent. No competing traffic on the
internal buses is considered.
These latencies comprehend only those from the time an IA initiated transaction is
received at the AIOC to the time the AIOC completes the transaction. No IA, FSB, MCH,
software, etc latencies are included.
Table 42-11 provides example estimates for various platform configurations.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1704
August 2009
Order Number: 320066-003US