EP80579 Datasheet, PDF (320/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Figure 12-6. Source in Decrement and Destination in Increment Mode Transfer (Byte
Reversal)
MSB
Memory
LSB
ADDRESS
64-bit Source
Data Block
Transfer
7
6
5
4
3
2
1
A000 0200H
15
14
13
12
11
10
9
8
A000 0208H
20
19
18
17
16
A000 0210H
20
12
64-bit Destination
4
Programmed Values
EDMACTL 0000 0088H
SUAR/SAR _{A000 0214H}
DUAR/DAR 4001 0307H
TCR _{0000 0014H}
DCR 0000 101FH
4001 0300H
13
14
15
16
17
18
19
4001 0308H
5
6
7
8
9
10
11
4001 0310H
1
2
3
4001 0318H
10
byte number
Bus Operation
SOURCE
QWORD load@A0000210
QWORD load@A0000208
QWORD load@A0000200
DESTINATION
Byte store@40010307
QWORD store@40010308
QWORD store@40010310
3-Byte store@40010318
B4485-01
12.5.2.3
Constant Address Modes
In constant address mode, there is built-in support for “mailbox” destinations in the
memory mapped I/O subsystem. A mailbox is a single or limited set of addresses used
to collect information for dispersal later to their actual destination addresses by the
receiving device. In constant address mode, one, two, or four bytes will be sent
repeatedly until the byte count is satisfied.
The source address can be byte aligned; however, unlike other transfer modes, in
constant address Mode the destination address must be aligned to the granularity size.
No errors will be flagged if the destination address is not matched to the granularity,
but the required lower address bits will be ignored. Additionally, software must ensure
that the transfer byte count is an integer multiple of the granularity size. No error will
be flagged if the transfer byte count is not an integer multiple and the remaining bytes
in the requested granularity will be padded and transferred.
Intel^® EP80579 Integrated Processor Product Line Datasheet
320
August 2009
Order Number: 320066-003US