EP80579 Datasheet, PDF (414/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.1.1.29 Offset BCh: IMCH_MENCLIMIT - IA/ASU Shared Non-Coherent (AIOC-
Direct) Memory Limit Address Register
Table 16-31. Offset BCh: IMCH_MENCLIMIT - IA/ASU Shared Non-Coherent (AIOC-Direct)
Memory Limit Address Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: BCh
Offset End: BFh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 20
19 : 00
Bit Acronym
Bit Description
Sticky
Reserved
MENCLIMIT
Reserved
IA/ASU Shared Non-Coherent Memory Limit Address
Bits[31:12]: Specifies the address of the upper boundary
of the IA/ASU shared non-coherent window in 32-bit
system address space. The window is 4KB-aligned and
inclusive of this address. This register field specifies
bits[31:12] of the address; bits[11:0] are assumed ones.
Setting IMCH_MENCLIMIT less than IMCH_MENCBASE
indicates a zero-sized window and thus that all memory is
coherent.
Bit Reset
Value
00h
00000h
Bit Access
RW
16.1.1.30 Offset C4h: TOLM - Top of Low Memory Register
This register contains the maximum address below 4 Gbyte that must be treated as a
memory access and is defined on a 128 Mbyte boundary. Usually it is below the areas
configured for PCI Express, NSI, and PCI memory. The memory address found in DRB3
reflects the amount of total memory populated.
Intel^® EP80579 Integrated Processor Product Line Datasheet
414
August 2009
Order Number: 320066-003US