EP80579 Datasheet, PDF (1161/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 32-6. Offset 100h: HPTCC[0-2] - Timer n Configuration and Capabilities Register
(Sheet 3 of 3)
Description:
Timer 0:
+ 107h
100 – 107h, Timer 1:
120 – 127h, Timer 2:
140 – 147h, Timer n:
(20h * n) +100h
-
(20h * n)
View: IA F
Base Address: HPTC
Offset Start: 100h at 20h
Offset End: 107h at 20h
Size: 64 bit
Default: Xh
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
Timer n Type: (where n is the timer number: 00 to 31).
Timer 0:Bit is read/write.
03
TIMERn_
TYPE_CNF
0 = Disable timer to generate a periodic interrupt.
1 = Enable timer to generate a periodic interrupt.
Timers 1, 2: Hardwired to 0. so bit access is Read Only.
Timer n Interrupt Enable: (where n is the timer
number: 00 to 31). This bit must be set to enable timer n
02
TIMERn_INT_EN ^{to cause an interrupt when it times out.}
B_CNF
0 = Disable. The timer still counts but does not cause an
interrupt.
1 = Enable.
Timer Interrupt Type: (where n is the timer number: 00
to 31)
0 = The timer interrupt is edge triggered. This means
that an edge-type interrupt is generated. If another
interrupt occurs, another edge is generated.
01
TIMERn_INT_TY ^{1 = The timer interrupt is level triggered. This means that}
PE_CNF
a level-triggered interrupt is generated. The interrupt
is held active until it is cleared by writing to the bit in
the General Interrupt Status Register. If another
interrupt occurs before the interrupt is cleared, the
interrupt remains active.
Bit Reset
Value
Xh
0h
0h
Bit Access
RW or RO
RW
RW
00
Reserved Reserved: This bit returns zero when read.
0h
RO
Note: Reads or writes to unimplemented timers must not be attempted. Reads from any unimplemented registers return an
undetermined value.
32.2.1.6
Offset 108h: HPTCV[0-2] - Timer n Comparator Value Register
General Behavioral Rules:
• Software can access the various bytes in this register using 32-bit or 64-bit
accesses.
• 32-bit accesses can be done to offset 1x8h or 1xCh. 64-bit accesses can be done to
1x8h.
• 32-bit accesses must not be done to 1x9h, 1xAh, 1xBh, 1xDh, 1xEh, or 1xFh.
• Reads to this register return the current value of the comparator.
• If the timer is configured to non-periodic mode:
— Writes to this register load the value against which the main counter must be
compared for this timer.
— When the main counter equals the value last written to this register, the
corresponding interrupt can be generated (if so enabled).
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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