EP80579 Datasheet, PDF (1024/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Note:
26.6.1.2
10. The PDE implements a “Gross Late-Start” check which determines whether any
more control or data structure reads will be initiated for transactions associated
with the current microframe. The threshold for this check is determined by the
Gross Late Start Cut-Off field in configuration register offset 84h.
11. An entry in the 2-deep command FIFO becomes available for a new transaction
fetch when any of the following events occur:
a. The final transaction results are posted in write buffers to memory.
b. Either of the late-start checks fail for this transaction (or the preceding
transaction in the same microframe).
c. A High-Bandwidth Interrupt transaction times out. For High-Bandwidth
Interrupt transactions that time out, the CMI does not immediately retry the
transaction as recommended by the USB Specification (Section 5.9.1). Instead,
all control and data structures are flushed and the transaction is reattempted
the next time that endpoint is scheduled.
When a host error occurs, the commands are kept in the PDE. The EHCI software driver
must assert the HCRESET in order to clear the pending transactions before reenabling
the PDE.
12. Data fetches are not initiated unless there is room in the Out Data FIFO to consume
the amount of data requested.
13. Read requests are broken up and throttled based on the Read Request Maximum
Length field and the Request Rate Throttle fields in the configuration register at
offset FCh. Control or Data structures that cross a Maximum Length-aligned
boundary in memory are broken into multiple requests. This allows other packets
from within the IICH to be interleaved on the IMCH/IICH link and through the
memory controller to avoid temporary starvation of those functions. When
generating the multiple read requests, the EHC will naturally-align the requests
(i.e., 64-byte requests will not fetch across 64-byte address boundaries in
memory). This guarantees that, as cache-line sizes increase, the back-to-back
requests do not cause double-snoops on specific cache lines. Unlike control
structure read requests, only reads for data will be subject to the Request Rate
Throttle.
14. Asynchronous DMA memory accesses may be interleaved at any point with the
periodic DMA memory accesses on the IMCH/IICH link.
Write Policies for Periodic DMA
The Periodic DMA engine performs writes to the following data structures:
Periodic DMA write policies:
1. The Periodic DMA Engine (PDE) will only generate writes after a transaction is
executed on USB. Some important notes associated with this rule are:
a. If either of the late-start checks fails before the transaction is run on the USB
ports, then none of the writes normally associated with that transaction will
occur. High-Bandwidth Exception: If the late-start check fails after the first
packet of a High-Bandwidth (multi) transaction is executed but before the last
packet, then the PDE must write the status for any completed transfers to
memory.
b. The Queue Head Overlay write occurs after the first transaction for a qTD is
completed on the USB interface.
2. Status writes are always performed after In Data writes for the same transaction.
3. When writing the status back to the two siTDs associated with a backpointer, the
PDE first writes to the siTD which was referenced by the backpointer and secondly
writes to the siTD which contains the backpointer.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1024
August 2009
Order Number: 320066-003US