EP80579 Datasheet, PDF (1075/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 27-23. Offset 44h: DEVTRAP_STS - DEVTRAP_STS Register (Sheet 2 of 2)
Description:
View: PCI
BAR: PMBASE (IO)
Bus:Device:Function: 0:31:0
Offset Start: 44h
Offset End: 44h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
08
07
06
05 : 00
Bit Acronym
Bit Description
Sticky
D8_TRP_STS
PIRQ[C or G]:
0 = The corresponding PCI interrupts have not been
active.
1 = At least one of the corresponding PCI interrupts
has been active. Clear this bit by writing a 1 to the
bit location.
D7_TRP_STS
PIRQ[B or F]:
0 = The corresponding PCI interrupts have not been
active.
1 = At least one of the corresponding PCI interrupts
has been active. Clear this bit by writing a 1 to the
bit location.
D6_TRP_STS
PIRQ[A or E]:
This bit will be set if PCI IRQ A or PCI IRQ E goes active
(by the pin or internal signal).
0 = The corresponding PCI interrupts have not been
active.
1 = At least one of the corresponding PCI interrupts
has been active. Clear this bit by writing a 1 to the
bit location.
Reserved Reserved
Bit Reset
Value
0h
0h
0h
0h
Bit Access
RWC
RWC
RWC
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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