EP80579 Datasheet, PDF (477/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.2.1.30 Offset 78h: BUF_SCICMD - Memory Buffer SCI Command Register
This register enables various errors to generate an SCI NSI special cycle. When an
error flag is set in the FERR or NERR registers, it generates an SCI NSI special cycle
when enabled in the SCICMD registers. Note that one and only one message type can
be enabled.
Table 16-84. Offset 78h: BUF_SCICMD - Memory Buffer SCI Command Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:1
Offset Start: 78h
Offset End: 78h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
07 : 04
03
02
01
00
Reserved Reserved
DPMWB_SCI
Internal DRAM Interface to PMWB Parity Error SCI
Enable: Generate SCI when parity error detected for
DRAM Interface to PMWB when this bit is set.
0 = Disable
1 = Enable
IOPMWB_SCI
Internal System Bus or I/O to PMWB Parity Error SCI
Enable: Generate SCI when parity error detected for
internal System Bus or I/O to PMWB when this bit is set.
0 = Disable
1 = Enable
Internal PMWB to System Bus Parity Error SCI
Enable: Generate SCI when parity error detected for
PMWBSYS_SCI ^{PMWB to System Bus when this bit is set.}
0 = Disable
1 = Enable
PMWBD_SCI
Internal PMWB to DRAM I/F Parity Error SCI Enable:
Generate SCI when parity error detected for PMWB to
DRAM I/F when this bit is set.
0 = Disable
1 = Enable
Bit Reset
Value
0h
0b
0b
0b
0b
Bit Access
RW
RW
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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