EP80579 Datasheet, PDF (457/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.2.1.15 Offset 4Ch: NSI_NERR - NSI Next Error Register
Errors that are detected after the first error are captured by this register.
Table 16-69. Offset 4Ch: NSI_NERR - NSI Next Error Register (Sheet 1 of 3)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:1
Offset Start: 4Ch
Offset End: 4Fh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 30
29
28
27
26
25
24
23
22
21
20
19
Bit Acronym
Bit Description
Sticky
Reserved
UR
Reserved
MTLP
ROVF
UEC
CA
CT
Reserved
PTLP
Reserved
DLPE
Reserved
Unsupported Request: This bit is sticky through reset.
0 = Cleared by writing a ‘1’ to the bit location.
1 = Unsupported Request detected.
Reserved
Malformed TLP Status: Malformed TLP errors include:
data payload length issues, byte enable rule violations, and
various other illegal field settings. This bit is sticky through
reset.
0 = Cleared by writing a ‘1’ to the bit location.
1 = Malformed TLP detected.
Receiver Overflow Status: IMCH checks for overflows on
the following upstream queues: posted, non-posted, and
completion. This bit is sticky through reset.
0 = Cleared by writing a ‘1’ to the bit location.
1 = Receiver Overflow detected.
Unexpected Completion Status: This bit is set when the
device receives a completion which does not correspond to
any of the outstanding requests issued by that device. This
bit is sticky through reset.
0 = Cleared by writing a ‘1’ to the bit location.
1 = Unexpected Completion detected.
Completer Abort Status: If a request received violates
the specific programming model of this device, but is
otherwise legal, this bit is set. This bit is sticky through
reset.
0 = Cleared by writing a ‘1’ to the bit location.
1 = Completer Abort detected.
Completion Timeout Status: The Completion Timeout
timer must expire if a Request is not completed in 50 ms,
but must not expire earlier than 50 µs. When the timer
expires, this bit is set. This bit is sticky through reset.
0 = Cleared by writing a ‘1’ to the bit location.
1 = Completion timeout detected.
Reserved
Poisoned TLP Status: This bit when set indicates that
some portion of the TLP data payload was corrupt. This bit
is sticky through reset.
0 = Cleared by writing a ‘1’ to the bit location.
1 = Poisoned TLP detected.
Reserved
Data Link Protocol Error Status: This bit is set when an
ACK/NAK received does not specify the sequence number
of an unacknowledged TLP, or of the most recently
acknowledged TLP. This bit is sticky through reset.
0 = Cleared by writing a ‘1’ to the bit location.
1 = Data Link Protocol Error detected.
Bit Reset
Value
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
Bit Access
RWC
RWC
RWC
RWC
RWC
RWC
RWC
RWC
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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