EP80579 Datasheet, PDF (1227/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
34.2.2.25 Offset 30h: IOBU – I/O Base Upper Register
This register provides the upper 16 bits for IOB.
Table 34-27. Offset 30h: IOBU: I/O Base Upper Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:4:0
Offset Start: 30h
Offset End: 31h
Size: 16 bit
Default: 0
Power Well: Core
Bit Range
15 : 00
Bit Acronym
Bit Description
IOBU
These bits correspond to address bits [31:16] of the I/O
transaction.
Sticky
Bit Reset
Value
0h
Bit Access
RO
34.2.2.26 Offset 32h: IOLU – I/O Limit Upper Register
This register provides the upper 16 bits for IOL.
Table 34-28. Offset 32h: IOLU: I/O Limit Upper Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:4:0
Offset Start: 32h
Offset End: 33h
Size: 16 bit
Default: 0
Power Well: Core
Bit Range
15 : 00
Bit Acronym
Bit Description
IOLU
These bits correspond to address bits [31:16] of the I/O
transaction.
Sticky
Bit Reset
Value
0h
Bit Access
RO
34.2.2.27 Offset 34h: CP – Capabilities Pointer Register
Table 34-29. Offset 34h: CP: Capabilities Pointer Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:4:0
Offset Start: 34h
Offset End: 34h
Size: 8 bit
Default: dch
Power Well: Core
Bit Range Bit Acronym
Bit Description
07 : 00
CP
Capabilities Pointer
Sticky
Bit Reset
Value
DCh
Bit Access
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1227