EP80579 Datasheet, PDF (1271/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
35.8.1.13 Offset DDh: PCP – Power Management Next Capability Pointer
Register
The Power Management Capability record controls power management in the device. It
is a 6B PCI SIG-defined capability record and includes the PCID, PCP, PMCAP, and PMCS
fields of the configuration header.
For an overview of the power management capability of AIOC devices, see Section
35.5, “Power Management of AIOC Devices”.
Table 35-56. Offset DDh: PCP: Power Management Next Capability Pointer Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:3:0
Offset Start: DDh
Offset End: DDh
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
PCP
Next Capability Pointer: Hardwired to 0 to indicate this
is the last capability.
Bit Reset
Value
0h
Bit Access
RO
35.8.1.14 Offset DEh: PMCAP – Power Management Capability Register
For an overview of the power management capability of AIOC devices, see Section
35.5, “Power Management of AIOC Devices”.
Table 35-57. Offset DEh: PMCAP: Power Management Capability Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:3:0
Offset Start: DEh
Offset End: DFh
Size: 16 bit
Default: 0023h
Power Well: Core
Bit Range Bit Acronym
Bit Description
15 : 11
10
09
08 : 06
05
04
03
02 : 00
PME_SPT
D2_SPT
D1_SPT
AUX_CRNT
DSI
Reserved
PME_CLI
VER
PME# Support
D2 Support
D1 Support
Aux Current
Device Specific Initialization
Reserved
PME Clock
Version
Sticky
Bit Reset
Value
0h
0h
0h
0h
1
0h
0h
011b
Bit Access
RO
RO
RO
RO
RO
RV
RO
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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