EP80579 Datasheet, PDF (10/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
13.6 IMCH I/O Mapped Registers .............................................................................. 354
13.6.0.1 Offset 0CF8h: CONFIG_ADDRESS - Configuration Address Register ........ 354
13.6.0.2 Offset 0CFCh: CONFIG_DATA - Configuration Data Register .................. 355
13.7 IMCH Memory Mapped Registers ........................................................................ 355
13.8 PCI Express Enhanced Configuration Mechanisms................................................. 356
13.8.1 PCI Express Configuration Transaction Header ............................................ 356
13.8.2 Enhanced Configuration Hardware Implications........................................... 356
13.8.3 Enhanced Configuration Memory Address Map ............................................ 357
13.8.4 Enhanced Configuration FSB Address Format.............................................. 357
14.0 RAS Features and Exception Handling .................................................................... 359
14.1 RAS Features .................................................................................................. 359
14.1.1 Data Protection ...................................................................................... 359
14.1.1.1
14.1.1.2
14.1.1.3
DRAM ECC ..................................................................................... 359
PCI Express Interface ...................................................................... 359
Data Error Propagation Between Interfaces/Units ................................ 359
14.1.2 DRAM Data Integrity ............................................................................... 360
14.1.2.1
14.1.2.2
14.1.2.3
14.1.2.4
14.1.2.5
Periodic Memory Scrubbing............................................................... 360
DRAM Hardware Initialization ............................................................ 360
Uncorrectable Retries....................................................................... 360
DRAM Refresh................................................................................. 361
DDR I/O Hardware Assisted Calibration .............................................. 361
14.1.3 PCI Express Data Integrity ....................................................................... 361
14.1.3.1
14.1.3.2
14.1.3.3
14.1.3.4
PCI Express Training........................................................................ 361
PCI Express Retry ........................................................................... 361
PCI Express Recovery ...................................................................... 361
PCI Express Retrain ......................................................................... 361
14.1.4 Test/Support Major Buses........................................................................ 362
14.1.4.1
14.1.4.2
14.1.4.3
14.1.4.4
IICH XOR ....................................................................................... 362
SMB (IMCH) ................................................................................... 362
SMB (IICH) .................................................................................... 362
I2C ............................................................................................... 362
14.2 Exception Handling .......................................................................................... 362
14.2.1 FERR/NERR Global Register Scheme ......................................................... 362
14.2.1.1
14.2.1.2
14.2.1.3
14.2.1.4
14.2.1.5
14.2.1.6
14.2.1.7
14.2.1.8
14.2.1.9
FERR/NERR Unit Registers ................................................................ 363
Clearing FERR/NERR Registers .......................................................... 363
FERR/NERR Unit Specific .................................................................. 364
SERR/SMI/SCI Enabling Registers...................................................... 364
MCERR Enabling Registers ................................................................ 365
Error Escalation Register .................................................................. 365
Error Masking ................................................................................. 365
PCI Express Errors and Errors on Behalf of PCI Express ........................ 366
Configurable Error Containment at the Legacy Interface ....................... 367
14.3 Error Conditions Signaled.................................................................................. 368
15.0 Platform Management (IMCH) ............................................................................... 371
15.1 Integrated SMBus Interface............................................................................... 371
15.2 SMBus Target Architecture ................................................................................ 371
15.2.1 High Level Operation............................................................................... 371
15.2.1.1
15.2.1.2
15.2.1.3
15.2.1.4
15.2.1.5
SMBus Register Summary ................................................................ 371
Internal Register Access Mechanism .................................................. 373
SMBus Register Definitions ............................................................... 373
Unsupported Access Addresses ......................................................... 376
SMBus Transaction Pictograms ......................................................... 376
15.2.2 Suggested SMBus Usage Models ............................................................... 380
15.2.2.1 Remote Error Handling..................................................................... 380
15.2.2.2 Remote Platform Monitoring ............................................................. 380
15.3 Platform Power Management Support ................................................................. 380
Intel^® EP80579 Integrated Processor Product Line Datasheet
10
August 2009
Order Number: 320066-003US