EP80579 Datasheet, PDF (741/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
19.2.2.4 Offset 4Ch: GC: GPIO Control Register
Table 19-13. Offset 4Ch: GC: GPIO Control Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:0
Offset Start: 4Ch
Offset End: 4Ch
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 :05
04
03 :00
Bit Acronym
Bit Description
Sticky
Reserved
EN
Reserved
Reserved.
GPIO Enable: This bit enables/disables decode of the I/O
range pointed to by the GPIO Base Address register (D31,
F0, 48h) and enables the GPIO function.
0 = Disable
1 = Enable
Reserved.
Bit Reset
Value
000h
0h
0000h
Bit Access
RW
19.2.3
19.2.3.1
Interrupt Configuration Registers
Offset 60h: PARC: PIRQA Routing Control Register
Table 19-14. Offset 60h: PARC: PIRQA Routing Control Register
Description: PARC - Routing Control Register.
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:0
Offset Start: 60h
Offset End: 60h
Size: 8 bit
Default: 80h
Power Well: Core
Bit Range
07
06 :04
03 :00
Bit Acronym
Bit Description
Sticky
REN
Reserved
IR
Interrupt Routing Enable:
0 = The corresponding PIRQ is routed to one of the legacy
interrupts specified in bits[03:00].
1 = The PIRQ is not routed to the 8259.
Note: BIOS must program this bit to 0 during POST for
any of the PIRQs that are being used. The value
of this bit may subsequently be changed by the
OS when setting up for I/O APIC interrupt
delivery mode.
Reserved
IRQ Routing:
Bits Mapping
0000 Reserved
0001 Reserved
0010 Reserved
0011 IRQ3
0100 IRQ4
0101 IRQ5
0110 IRQ6
0111 IRQ7
Bits
1000
1001
1010
1011
1100
1101
1110
1111
Mapping
Reserved
IRQ9
IRQ10
IRQ11
IRQ12
Reserved
IRQ14
IRQ15
Bit Reset
Value
1
000h
0h
Bit Access
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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