EP80579 Datasheet, PDF (166/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
IMCH can also configure some aspects of the IA-32 core at Power On. IMCH drives
these configuration settings before CPURST# (internal signal) assertion based on the
contents of its Power-On Configuration Register (D8, F0, offset C0h).
IMCH Signals
Inputs
PWRGD - IMCH PowerGood: This signal is directly connected to the platform
signal, SYS_PWR_OK. When asserted, PWRGD is an indication to the IMCH that
power has been stable for at least 99 ms. When PWRGD is inactive, the IMCH
asserts its CPURST# (internal signal) outputs.
RSTIN# - IMCH Reset: This signal is directly connected to the IICH PLTRST#
output. When RSTIN is active, the IMCH asserts its CPURST# (internal signal)
output.
6.1.2.3.3
6.1.2.3.4
6.1.2.3.5
IA-32 core
Early in the cold reset (powergood) sequence, the IA-32 core voltage regulator drives a
default voltage to the IA-32 core to read the fuses containing the IA-32 core FSB
frequency requirements. The EP80579 then drives its BSEL pin to the appropriate value
which is latched by the platform when it is known to be stable. The platform uses the
BSEL information to update the IA-32 core voltage regulator to the appropriate
operating voltage prior to the assertion of CPU_VRD_PWR_GD. The platform also uses
the value of BSEL to drive the clock generator to the correct reference clock (BCLK)
frequency.
Reset and configuration for IA-32 core is done by IICH and IMCH. Reset for IA-32 core
starts when IMCH asserts CPURST# (internal signal) and IICH asserts CPUPWRGD. The
assertion of both of these signals initiates the PLL locking process for the IA-32 core. All
the flops and internal states are reset during the reset process. The processor’s PLL
locks before CPURST# (internal signal) is de-asserted. CPURST# (internal signal)
needs to be asserted for at least 1ms and not more than 10ms (processor spec).The
IA-32 core receives power-on configuration values on its address pins during CPURST#
(internal signal).
IMCH
The IMCH receives the central reset (PLTRST#) from IICH. Clocks to DIMMs are
disconnected till BIOS configures the DIMMs. Memory controller core logic boots at the
default frequency as driven by the BSEL pin. Based on the DDR type and frequency
memory controller needs to re-lock itself at the DDR frequency once BIOS has read the
DDR.
GbE MAC
There are three GbE MAC devices. Each GbE receives the internal system reset. Each
GbE also receives a power OK signal from the platform that is also used as a reset.
GbE0 receives this signal via the GBE_AUX_PWR_GOOD external pin. GbE1 and GbE2
receive this signal via the SYS_PWR_OK external pin. The SYS_PWR_OK pin is
connected to the SYS_PWR_OK platform signal which is also connected to the PWROK
and PWRGD pins. The GBE_AUX_PWR_GOOD pin should be connected to SYS_PWR_OK
when no auxiliary power supply is used. If an auxiliary supply is used for GbE0, then
GBE_AUX_PWR_GOOD should be connected to the power good signal from that power
supply (this signal is subject to the timing requirements documented in Figure 6-4,
“Power Rail Sequence Timings (Sustain Well Power Management)” on page 170).
Under all circumstances, GbE0 MUST be powered by either the system supply or the
auxiliary supply. Likewise, GBE_AUX_PWR_GOOD MUST be connected to the
corresponding power good signal. GbE0 must be powered to enable operation of either
GbE1 or GbE2.
Intel^® EP80579 Integrated Processor Product Line Datasheet
166
August 2009
Order Number: 320066-003US