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Intel^® EP80579 Integrated Processor
10.1.8 High SMM Memory Space
Table 10-10. High SMM Memory Space
From
HIGHSMM
0_FEDA_0000
To
0_FEDB_FFFF
The HIGHSMM space allows cacheable access to the compatible SMM space by
remapping valid SMM accesses between 0_FEDA_0000 and 0_FEDB_FFFF to physical
accesses between 0_000A_0000 and 0_000B_FFFF. The accesses are remapped when
SMRAM space is enabled, an appropriate access is detected on the processor bus, and
when EXSMRC.H_SMRAME (Section 16.1.1.25) allows access to high SMRAM space.
Inbound SMM memory accesses from any port are specially terminated; reads are
provided with data retrieved from address 0, while writes are ignored entirely (all byte
enables deasserted).
10.1.9
Note:
PCI Device Memory (MMIO)
The IMCH provides two distinct regions of memory that may be mapped to populated
PCI devices. The first is the traditional (non-prefetchable) MMIO range, which must lie
below the 4 GByte boundary. The registers associated with non-prefetchable MMIO
(MBASE/MLIMIT, see Section 16.4.1.17, “Offset 20h: MBASE - Memory Base Address
Register”/Section 16.4.1.18, “Offset 22h: MLIMIT - Memory Limit Address Register”)
are unchanged from historical 32-bit architecture IMCH implementations. The second is
the prefetchable MMIO range, which has been extended in CMI such that it may lie on
either side of the 4 GByte boundary. The registers associated with prefetchable MMIO
(PMBASE/PMLIMIT, see Section 16.4.1.19, “Offset 24h: PMBASE - Prefetchable Memory
Base Address Register”/Section 16.4.1.20, “Offset 26h: PMLIMIT - Prefetchable
Memory Limit Address Register”) have been augmented by the PCI defined upper 32-
bit base/limit register pair (PMBASU/PMLMTU, see Section 16.4.1.21, “Offset 28h:
PMBASU - Prefetchable Memory Base Upper Address Register”/Section 16.4.1.22,
“Offset 2Ch: PMLMTU - Prefetchable Memory Limit Upper Address Register”), although
only the first nibble of each register is implemented in the IMCH.
The MBASE/MLIMIT pair must be programmed to lie between TOLM and 4 GBytes. The
PMBASE/PMLIMIT and PMBASU/PMLMTU registers must be programmed to lie between
TOLM and 4 GBytes.
Because these registers define a PCI memory space, they are subject to the memory
access enable (MAE) control bit in the standard PCI command register (see Section
16.4.1.4, “Offset 04h: PCICMD - PCI Command Register”).
Using the same address space as both cacheable and non cacheable is discouraged.
Also, assigning and writing the same host address space to two independent
downstream devices is also discouraged. Although not illegal, both of the above
conditions are very difficult to setup intelligently and validate. If 2 devices decide to use
the same memory space, and they both send write cycles to it (both either cacheable
or uncacheable), there are no guarantees that device 1 data (being older) will get there
before device 2 data (being newer) if they do not use a flagging mechanism.
Intel^® EP80579 Integrated Processor Product Line Datasheet
276
August 2009
Order Number: 320066-003US