EP80579 Datasheet, PDF (790/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
21.4.2.1 Offset 3020h: SPIS – SPI Status
Table 21-5. Offset 3020h: SPIS - SPI Status
Description:
View: PCI
BAR: RCBA
Bus:Device:Function: 0:31:0
Offset Start: 3020h
Offset End: 3021h
Size: 16 bit
Default: 0001h
Power Well: Core
Bit Range
15
14 :4
3
2
1
0
Bit Acronym
Bit Description
Sticky
SCL
Rsvd
BAS
CDS
Rsvd
SCIP
SPI Configuration Lock-Down: When set to 1, the SPI
Static Configuration information in offsets 50h through 6Bh
can not be overwritten. Once set to 1, this bit can only be
cleared by a hardware reset.
Reserved
Blocked Access Status: Hardware sets this bit to 1 when
an access is blocked from running on the SPI interface due
to one of the protection policies or when any of the
programmed cycle registers are written while a
programmed access is already in progress. This bit is set
for both programmed accesses and direct memory reads
that get blocked. This bit remains asserted until cleared by
software writing a 1 or hardware reset.
Cycle Done Status: The EP80579 sets this bit to 1 when
the SPI Cycle completes
(i.e., SCIP bit is 0) after software sets the GO bit. This bit
remains asserted until cleared by software writing a 1 or
hardware reset. When this bit is set and the SPI bit in
Offset 3022h: SPIC – SPI Control is set, an internal signal
is asserted to the SMI# generation block. Software must
make sure this bit is cleared prior to enabling the SPI SMI#
assertion for a new programmed access.
This bit gets set after the Status Register Polling sequence
completes after reset deasserts. It is cleared before and
during that sequence.
Reserved.
SPI Cycle In Progress (SCIP): Hardware sets this bit
when software sets the SPI Cycle Go bit in the Offset
3022h: SPIC – SPI Control. This bit remains set until the
cycle completes on the SPI interface. Hardware
automatically sets and clears this bit so that software can
determine when read data is valid and/or when it is safe to
begin programming the next command. Software must
only program the next command when this bit is 0.
This bit reports 1b during the Status Register Polling
sequence after reset deasserts; it is cleared when that
sequence completes.
Bit Reset
Value
0
0
0
0
0
1
Bit Access
RWL
RV
RWC
RWC
RV
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
790
August 2009
Order Number: 320066-003US