EP80579 Datasheet, PDF (898/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 24-5. Offset 04h: CMD: Command Register (Sheet 2 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:3
Offset Start: 04h
Offset End: 05h
Size: 16 bit
Default: 0000h
Power Well: Resume
Bit Range
08
07
06
05 : 01
00
Bit Acronym
Bit Description
Sticky
SERR_EN
WCC
PER
Reserved
IOSE
SERR# Enable:
0 = Disables SERR# generation
1 = Enables SERR# generation
Wait Cycle Control: Reserved as ‘0’.
Parity Error Response:
0 = Disable
1 = Sets Detected Parity Error bit (D3, F3, 06, bit 15)
when a parity error is detected.
Reserved
I/O Space Enable:
0 = Disables access to the SM Bus I/O space registers as
defined by the Base Address Register
1 = Enables access to the SM Bus I/O space registers as
defined by the Base Address Register
Bit Reset
Value
0b
0b
0b
00h
0b
Bit Access
RW
RW
RW
24.2.1.4 Offset 06h: DS – Device Status Register
Table 24-6. Offset 06h: DS – Device Status Register (Sheet 1 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:3
Offset Start: 06h
Offset End: 07h
Size: 16 bit
Default: 0280h
Power Well: Resume
Bit Range
15
14
13
12
11
10 : 09
Bit Acronym
Bit Description
Sticky
DPE
SSE
RMA
RTA
STA
DEVT
Detected Parity Error:
0 = No parity error detected
1 = Parity error detected
Signaled System Error:
0 = No system error detected
1 = System error detected
Received Master Abort: Reserved as ‘0’.
Received Target Abort: Reserved as ‘0’.
Signaled Target-Abort Status:
0 = Did not terminate transaction for this function with a
target abort
1 = The function is targeted with a transaction that
terminates with a target abort
DEVSEL# Timing Status: This 2-bit field defines the
timing for DEVSEL# assertion. These read-only bits
indicate the DEVSEL# timing when performing a positive
decode.
Note: The CMI generates DEVSEL# with medium time.
Note: It is not clear if a PCI master can write to SMBus
controller.
Bit Reset
Value
0h
0h
0h
0h
0h
01h
Bit Access
RWC
RWC
RO
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
898
August 2009
Order Number: 320066-003US