EP80579 Datasheet, PDF (1629/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 41-4. IEEE1588 Version 1 and IEEE1588-2008 PTP Message Formats
Offset in bytes
V1 Fields
32
Control
33
Reserved
34
Flags
35
IEEE1588-2008 Fields
Control
LogMessagePeriod
Table 41-5. Message Decoding for V1
Enumeration
PTP_SYNC_MESSAGE
PTP_DELAY_REQ_MESSAGE
PTP_FOLLOWUP_MESSAGE
PTP_DELAY_RESP_MESSAGE
PTP_MANAGEMENT_MESSAGE
reserved
Value
0
1
2
3
4
5-255
Note
Time stamp
Time stamp
Table 41-6. Message decoding for IEEE1588-2008
MessageId
PTP_SYNC_MESSAGE
PTP_DELAY_REQ_MESSAGE
PTP_PATH_DELAY_REQ_MESSAGE
PTP_PATH_DELAY_RESP_MESSAGE
Unused
PTP_FOLLOWUP_MESSAGE
PTP_DELAY_RESP_MESSAGE
PTP_PATH_DELAY_FOLLOWUP_MESSAGE
PTP_ANNOUNCE_MESSAGE
PTP_SIGNALLING_MESSAGE
PTP_MANAGEMENT_MESSAGE
Unused
Message Type
Event
Event
Event
Event
General
General
General
General
General
General
Value (hex)
0
1
2
3
4-7
8
9
A
B
C
D
E-F
Note
Time stamp
Time stamp
Time stamp
Time stamp
41.5.2
Time Stamping Operation
Time stamping means that the current value in the system time register is captured in
a second register, generally called a snapshot register.
The time stamping will occur when the appropriate conditions exist such as an auxiliary
input is received or when a particular type of message is transmitted or received by the
channel. Once a timestamp of system time is taken and locked, a unique indication for
the snapshot is set in the appropriate Event register. No further timestamps of that
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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