EP80579 Datasheet, PDF (692/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
17.1.1.3 Offset 0008h: VCAP2 - Virtual Channel Capability 2 Register
Table 17-5. Offset 0008h: VCAP2 - Virtual Channel Capability 2 Register
Description:
View: PCI
BAR: RCBA
Bus:Device:Function: 0:31:0
Offset Start: 0008h
Offset End: 000Bh
Size: 32bit
Default: 0001h
Power Well: Core
Bit Range
31 :24
23 :08
07 :00
Bit Acronym
Bit Description
Sticky
ATO
Reserved
AC
VC Arbitration Table Offset: Indicates that no table is
present for VC arbitration since it is fixed.
Reserved
VC Arbitration Capability: Indicates that the VC
arbitration is fixed in the root complex.
Bit Reset
Value
00h
0h
01h
Bit Access
RO
RO
17.1.1.4 Offset 000Ch: PVC - Port Virtual Channel Control Register
Table 17-6. Offset 000Ch: PVC - Port Virtual Channel Control Register
Description:
View: PCI
BAR: RCBA
Bus:Device:Function: 0:31:0
Offset Start: 000Ch
Offset End: 000Dh
Size: 16 bit
Default: 0h
Power Well: Core
Bit Range
15 :04
03 :01
00
Bit Acronym
Bit Description
Sticky
Reserved
AS
LAT
Reserved
VC Arbitration Select: Indicates which VC must be
programmed in the VC arbitration table. The root complex
takes no action on the setting of this field since there is no
arbitration table.
Load VC Arbitration Table: Indicates that the table
programmed must be loaded into the VC arbitration table.
This bit is defined as read/write with always returning 0 on
reads. Since there is no VC arbitration table in the root
complex, this bit can be built as read-only.
Bit Reset
Value
000h
0h
0h
Bit Access
RW
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
692
August 2009
Order Number: 320066-003US