EP80579 Datasheet, PDF (402/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.1.1.18 Offset 5Ah: PAM1 - Programmable Attribute Map 1 Register
This register controls the read, write, and shadowing attributes of the BIOS areas from
0C0000h-0C7FFFh.
Table 16-20. Offset 5Ah: PAM1: Programmable Attribute Map 1 Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 5Ah
Offset End: 5Ah
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 06
05 : 04
03 : 02
01 : 00
Bit Acronym
Bit Description
Sticky
Reserved
HIENABLE
Reserved
LOENABLE
Reserved
Attribute Register 0C4000-0C7FFF: This field controls
the steering of read and write cycles that address the BIOS
area from 0C4000 to 0C7FFF
Encoding Description
00
DRAM Disabled - All accesses are directed
to NSI.
01
Read-Only - All reads are serviced by DRAM.
All writes are forwarded to NSI.
10
Write-Only - All writes are sent to DRAM.
Reads are serviced by NSI.
11
Normal DRAM Operation - All reads and
writes are serviced by DRAM.
Reserved
Attribute Register 0C0000-0C3FFF: This field controls
the steering of read and write cycles that address the BIOS
area from 0C0000 to 0C3FFF.
Encoding Description
00
DRAM Disabled - All accesses are directed
to NSI.
01
Read-Only - All reads are serviced by DRAM.
All writes are forwarded to NSI.
10
Write-Only - All writes are sent to DRAM.
Reads are serviced by NSI.
11
Normal DRAM Operation - All reads and
writes are serviced by DRAM.
Bit Reset
Value
00b
00b
00b
00b
Bit Access
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
402
August 2009
Order Number: 320066-003US