EP80579 Datasheet, PDF (54/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

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Chip Select Address Allocation When There Are no 32-MByte Devices Programmed.. 1674
Expansion Bus Memory Sizing .......................................................................... 1674
Chip Select Address Allocation when a 32 Mbyte device is programmed ................. 1675
Expansion Bus I/O Wait Operation .................................................................... 1681
Expansion-Bus Write (Intel, Multiplexed Mode) ................................................... 1683
Expansion-Bus Read (Intel, Multiplexed Mode).................................................... 1683
Expansion-Bus Write (Intel-Simplex Mode, Synchronous Intel) ............................. 1684
Expansion-Bus Read (Intel, Simplex Mode) ........................................................ 1684
Intel Synchronous 8-word Read ........................................................................ 1685
Intel Synchronous One-Word Read.................................................................... 1686
Micron* ZBT Write/Read/Write ......................................................................... 1687
Expansion-Bus Write (Motorola*, Multiplexed Mode) ............................................ 1688
Expansion-Bus Read (Motorola*, Multiplexed Mode) ............................................ 1689
Expansion-Bus Write (Motorola*, Simplex Mode)................................................. 1690
Expansion-Bus Read (Motorola*, Simplex Mode) ................................................. 1690
Expansion-Bus Write (TI* HPI-8 Mode) .............................................................. 1691
Expansion-Bus Read (TI* HPI-8 Mode) .............................................................. 1692
Expansion-Bus Write (TI* HPI-16, Multiplexed Mode) .......................................... 1693
Expansion-Bus Read (TI* HPI-16, Multiplexed Mode) ........................................... 1694
Expansion-Bus Write (TI* HPI-16, Simplex Mode) ............................................... 1695
Expansion-Bus Read (TI* HPI-16, Simplex Mode)................................................ 1696
Serial Test Mode Entry for Write ....................................................................... 1722
Serial Test Mode Entry for Read........................................................................ 1722
FCBGA Package — Top and Side Views .............................................................. 1775
FCBGA Package — Front and Detail Views .......................................................... 1776
FCBGA Package — Bottom View........................................................................ 1777
G3 (Mechanical Off) to S0 Timings .................................................................... 1834
S0 to S1 to S0 Timing ..................................................................................... 1834
S0 to S5 to S0 Timings, S3_COLD ........................................................................ 1835
DQ and CB (ECC) Setup/Hold Relationship to/from DQS (Read Operation) .............. 1843
DQ and CB (ECC) Valid Before and After DQS (Write Operation)............................ 1843
Write Preamble Duration.................................................................................. 1844
Write Postamble Duration ................................................................................ 1844
Control Signals Valid before and after DDR_CK Rising Edge .................................. 1844
Clock Cycle Time ............................................................................................ 1844
Skew Between any System Memory Differential Clock Pair (DDR_CK/DDR_CK#) ..... 1845
DDR2 Command Clock High Time ..................................................................... 1845
DDR2 Command Clock Low Time ...................................................................... 1845
DDR2 Command Clock to DQS skew.................................................................. 1846
PCI Express* Transmitter Test Load .................................................................. 1851
PCI Express* Receiver Compliance Eye Diagram ................................................. 1851
PCI Express* Transmitter Compliance Eye Diagram ............................................. 1852
Differential Clock Waveform ............................................................................. 1853
Differential Clock Cross-Point Specification ......................................................... 1853
Clock Timing .................................................................................................. 1860
USB Rise and Fall Times .................................................................................. 1861
USB Jitter ...................................................................................................... 1862
USB EOP Width .............................................................................................. 1862
SMBus Transaction ......................................................................................... 1865
SMBus Timeout .............................................................................................. 1866
SPI Timing Diagram ........................................................................................ 1870
LPC Clock (PCICLK) Timing Diagram.................................................................. 1872
LPC Input Setup and Hold Timing Diagram ......................................................... 1873
LPC Valid Delay from Rising Clock Edge Diagram................................................. 1873
LPC Output Enable Delay Diagram .................................................................... 1873
Intel^® EP80579 Integrated Processor Product Line Datasheet
54
August 2009
Order Number: 320066-003US