EP80579 Datasheet, PDF (1255/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
35.6.1.23 Offset E6h: SBC – Signal Target Byte Count Register
Table 35-28. Offset E6h: SBC: Signal Target Byte Count Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: M:0:0
Offset Start: E6h
Offset End: E6h
View: PCI 2
BAR: Configuration
Bus:Device:Function: M:1:0
Offset Start: E6h
Offset End: E6h
View: PCI 3
BAR: Configuration
Bus:Device:Function: M:2:0
Offset Start: E6h
Offset End: E6h
Size: 8 bit
Default: 09h
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
SBC
Capability Record Byte Count: Hardwired to the number
of bytes in the vendor-specific capability record.
Bit Reset
Value
09h
Bit Access
RO
35.6.1.24 Offset E7h: STYP – Signal Target Capability Type Register
Table 35-29. Offset E7h: STYP: Signal Target Capability Type Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: M:0:0
Offset Start: E7h
Offset End: E7h
View: PCI 2
BAR: Configuration
Bus:Device:Function: M:1:0
Offset Start: E7h
Offset End: E7h
View: PCI 3
BAR: Configuration
Bus:Device:Function: M:2:0
Offset Start: E7h
Offset End: E7h
Size: 8 bit
Default: 01h
Power Well: Core
Bit Range Bit Acronym
Bit Description
07 : 00
STYP
Capability Record Type: Vendor assigned capability
record type (01h, EP80579 signal target capability)
Sticky
Bit Reset
Value
Bit Access
01h
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1255