EP80579 Datasheet, PDF (599/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.5
Memory Mapped I/O Registers for DRAM Controller
Table 16-220.Bus 0, Device 0, Function 0: Summary of IMCH SMRBASE Registers (Sheet 1
of 2)
Offset Start Offset End
Register ID - Description
Default
Value
00h
02h
40h
44h
48h at 1h
94h
98h
9Ch
A0h
A4h
A8h
C4h
B4h
B8h
C6h
BCh
C0h
C7h
CCh
D0h
D4h
D8h
DCh
E0h
F0h
F8h
C8h
E8h
ECh
140h
144h
01h
03h
43h
47h
48h at 1h
96h
9Bh
9Ch
A3h
A7h
ABh
C4h
B7h
BBh
C6h
BFh
C3h
C7h
CFh
D0h
D7h
DBh
DFh
E3h
F3h
FBh
CAh
EBh
EFh
143h
147h
“Offset 00h: NOTESPAD - Note (Sticky) Pad for BIOS Support Register” on
page 601
0000h
“Offset 02h: NOTEPAD - Note Pad for BIOS Support Register” on page 601
0000h
“Offset 40h: DCALCSR – DCAL Control and Status Register” on page 602
00000000h
“Offset 44h: DCALADDR - DCAL Address Register” on page 606
00000000h
“Offset 48h: DCALDATA[0-71] - DRAM Calibration Data Register” on page 607
00000000h
“Offset 94h: RCVENAC - Receiver Enable Algorithm Control Register” on page 611 180810h
“Offset 98h: DSRETC - DRAM Self-Refresh (SR) Extended Timing and Control
Register” on page 611
5c141400h
“Offset 9Ch: DQSFAIL1 - DQS Failure Configuration Register 1” on page 612
00h
“Offset A0h: DQSFAIL0 - DQS Failure Configuration Register 0” on page 613
00000000h
“Offset A4h: DRRTC00 - Receive Enable Reference Output Timing Control Register”
on page 615
06060606h
“Offset A8h: DRRTC01 - Receive Enable Reference Output Timing Control Register”
on page 616
06060606h
“Offset C4h: DRRTC02 - Receive Enable Reference Output Timing Control Register”
on page 616
06h
“Offset B4h: DQSOFCS00 - DQS Calibration Register” on page 617
00000000h
“Offset B8h: DQSOFCS01 - DQS Calibration Register” on page 617
00000000h
“Offset C6h: DQSOFCS02 - DQS Calibration Register” on page 618
00h
“Offset BCh: DQSOFCS10 - DQS Calibration Register” on page 618
00000000h
“Offset C0h: DQSOFCS11 - DQS Calibration Register” on page 619
00000000h
“Offset C7h: DQSOFCS12 - DQS Calibration Register” on page 619
00h
“Offset CCh: WPTRTC0 - Write Pointer Timing Control Register” on page 620
00000000h
“Offset D0h: WPTRTC1 - Write Pointer Timing Control 1 Register” on page 621
00h
“Offset D4h: DDQSCVDP0 - DQS Delay Calibration Victim Pattern 0 Register” on
page 621
aaaa0a05h
“Offset D8h: DDQSCVDP1 - DQS Delay Calibration Victim Pattern 1 Register” on
page 622
5b339c5dh
“Offset DCh: DDQSCADP0 - DQS Delay Calibration Aggressor Pattern 0 Register”
on page 622
aaabffffh
“Offset E0h: DDQSCADP1 - DQS Delay Calibration Aggressor Pattern 1 Register”
on page 623
db339ce1h
“Offset F0h: DIOMON - DDR I/O Monitor Register” on page 623
00000000h
“Offset F8h: DRAMISCTL - Miscellaneous DRAM DDR Cluster Control Register” on
page 624
1011h
“Offset C8h: DRAMDLLC - DDR I/O DLL Control Register” on page 625
0DB6C0h
“Offset E8h: FIVESREG - Fixed 5s Pattern Register” on page 625
55555555h
“Offset ECh: AAAAREG - Fixed A Pattern Register” on page 626
AAAAAAAAh
“Offset 140h: MBCSR - MemBIST Control Register” on page 626
00000000h
“Offset 144h: MBADDR - Memory Test Address Register” on page 629
00h
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
599