EP80579 Datasheet, PDF (1142/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
30.4
30.5
30.5.1
30.5.2
PCI Interrupts via /PCI Express*
When external devices through PCI Express* wish to generate an interrupt, they send
the message defined in the PCI Express* Specification for generating INTA# - INTD#.
These are translated into internal assertions/deassertions of INTA# - INTD#.
see Section 17.1.5, “Interrupt Configuration Registers” on page 701
Serial Interrupt
Overview
The IICH interrupt controller supports a serial IRQ scheme. This allows a single signal
to be used to report interrupt requests. The signal used to transmit this information is
shared between the interrupt controller and all peripherals that support serial
interrupts. The signal line, SERIRQ, is synchronous to the PCI clock, and follows the
sustained tri-state protocol that is used by legacy PCI signals. This means that if a
device has driven SERIRQ low, it first drives it high synchronous to the PCI clock and
releases it after the following PCI clock. The serial IRQ protocol defines this sustained
tri-state signaling in the following fashion:
• S - Sample Phase: Signal driven low.
• R - Recovery Phase: Signal driven high.
• T - Turn-around Phase: Signal released.
The IICH supports a message for 21 serial interrupts. These represent the 15 ISA
(legacy) interrupts (IRQ0-1, 3-15), the four PCI interrupts, and the control signals
SMI# and ISA (legacy) IOCHK#. The serial IRQ protocol does not support the
additional APIC interrupts (20–39). The serial interrupt information is transferred using
three types of frames:
• Start Frame: SERIRQ line driven low by the interrupt controller to indicate the
start of IRQ transmission.
• Data Frames: IRQ information transmitted by peripherals. The interrupt controller
supports 21 data frames.
• Stop Frame: SERIRQ line driven low by the interrupt controller to indicate end of
transmission and next mode of operation.
Start Frame
The serial IRQ protocol has two modes of operation which affect the start frame:
• Continuous Mode: The interrupt controller is solely responsible for generating the
start frame.
• Quiet Mode: Peripheral initiates the start frame, and the interrupt controller
completes it.
The mode that must first be entered when enabling the serial IRQ protocol is
continuous mode. In this mode, the IICH asserts the start frame. This start frame is
four, six, or eight PCI clocks wide based upon the Serial IRQ Control
Register(SCNT.SFPW) field, bits 01:00 at 64h in Device 31, Function 0 configuration
space. This is a polling mode.
When the serial IRQ stream enters quiet mode (signaled in the Stop Frame), the
SERIRQ line remains inactive and pulled up between the Stop and Start Frame until a
peripheral drives the SERIRQ signal low. The IICH senses the line low and continues to
drive it low for the remainder of the Start Frame. Since the first PCI clock of the start
Intel^® EP80579 Integrated Processor Product Line Datasheet
1142
August 2009
Order Number: 320066-003US