EP80579 Datasheet, PDF (1847/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 49-20. PCI Express* Differential Receiver (RX) Specifications
Symbol
Parameter
Min
Nom
Max
Unit
Figures Notes
Z_RX-DIFF-DC
Rx DC Differential Input
Impedance
80
100
120 Ohms
-
1
Z_RX-DC
Rx DC Input Common Mode
Impedance
40
50
60
Ohms
-
1, 2
Z_RX-HIGH-
IMP-DC
Rx Powered Down DC Input
Common Mode Impedance
200k
-
-
Ohms
-
3
UI
Unit Interval
399.88
400
400.12 ps
-
5
V_RX-DIFFp-p
Differential Peak-to-Peak Input
Voltage (at spec load)
0.175
-
1.2
V
49-15
6, 4
T_RX-EYE Minimum Receiver Eye Width
0.40
-
T_RX-EYE- Maximum time between the
MEDIAN-to- ^{jitter median and maximum}
-
-
MAX-JITTER ^{deviation from the median}
V_RX-CM-ACp
AC Peak Common Mode Input
Voltage
-
-
-
UI
0.3
UI
150
mV
49-15
-
-
6, 7
6, 7
6
RL_RX-DIFF Differential Return Loss
15
-
dB
-
8
RL_RX-CM Common Mode Return Loss
6
-
dB
-
8
V_RX-IDLE- Electrical Idle Detect
DET-DIFFp-p ^Threshold
65
-
175
mV
-
T_RX-IDLE-
DET-DIFF-
ENTERTIME
Unexpected Electrical Idle
Enter Detect Threshold
Integration Time
-
-
10
ms
-
L_RX-SKEW Total Skew
-
20
ns
-
Notes:
1.
Specified at the measurement point and measured over any 250 consecutive UIs. The test load in
Figure 49-14 (not the EP80579 itself) must be used as the Rx device when taking measurements
(also refer to the Receiver Compliance Eye Diagram as shown in Figure 49-15). If the clocks to the Rx
and Tx are not derived from the same clock chip the Tx UI must be used as a reference for the eye
diagram.
2.
Impedance during all LTSSM states. When transitioning from a Fundamental Reset to Detect (the
initial state of the LTSSM) there is a 5ms transition time before Receiver termination values must be
met on all un-configured Lanes of a Port.
3.
The Rx DC Common Mode Impedance that exists when no power is present or Fundamental Reset is
asserted. This helps ensure that the Receiver Detect circuit does not falsely assume a Receiver is
powered on when it is not. This term must be measured at 300mV above the Rx ground.
4.
PCI-Express mVdiff p-p = PEA0_Xp[x] - PEA0_Xn[x]
5.
No test load is necessarily associated with this value.
6.
Specified at the measurement point and measured over any 250 consecutive UIs. The test load in
Figure 49-14 and measured over any 250 consecutive Unit Intervals. Also refer to the Receiver
Compliance Eye Diagram as shown in Figure 49-15. That is, the receiver device must be replaced with
50 Ω terminations to ground on each half of the signal pair for the purpose of measuring this
parameter. If the clocks to the Rx and Tx are not derived from the same clock chip the Tx UI must be
used as a reference for the eye diagram.
7.
A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for
the transmitter and interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-
JITTER specification ensures a jitter distribution in which the median and the maximum deviation
from the median is less than half of the total.6 UI jitter budget collected over any 250 consecutive Tx
UIs. It must be noted that the median is not the same as the mean. The jitter median describes the
point in time where the number of jitter points on either side is approximately equal as opposed to
the averaged time value. If the clocks to the Rx and Tx are not derived from the same clock chip, the
appropriate average Tx UI must be used as the reference for the eye diagram.
8.
The receiver input impedance shall result in a differential return loss greater than or equal to 15 dB
and a common mode return loss greater than or equal to 6 dB over a frequency range of 50 MHz to
1.25 GHz. This input impedance requirement applies to all valid input levels. The reference
impedance for return loss measurements for is 50 Ω to ground for both the D+ and D– line (for
example, as measured by a Vector Network Analyzer with 50 Ω probes – see Figure 49-15). Note that
the series capacitors CTX is optional for the return loss measurement.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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