EP80579 Datasheet, PDF (1336/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
36.2.1
36.2.2
Power management features include support for APM and APCI. Each controller
supports the D0 and D3 states including internal clock gating for reduced power
consumption in the D3 state. Further, one controller is located in an independent
auxiliary power well for particularly power sensitive applications.
The DMA function provides the capability for packet data transfer and descriptor
management. The GbE controller is able to cache up to 64-packet descriptors. A
64-KByte, on-chip packet buffer maintains performance as available bandwidth
changes.
Finally, each controller is capable of self-configuration via an optional, external serial
EEPROM.
Integrated DMA Features
• Performs descriptor-driven receive packet transfers from Rx MAC to system
memory.
• Performs descriptor-driven transmit packet transfers from system memory to Tx
MAC.
• Separate transmit and receive DMA engines.
• 64-entry descriptor caches for transmit and receive.
• Descriptor ring management hardware.
• Configurable 64KB packet buffer.
MAC Features
The MAC controller’s SCSMA/CD unit handles all the IEEE 802.3 receive and transmit
MAC functions while interfacing between the DMA and link interface (RMII/RGMII) The
MAC unit supports:
• Complete CSMA/CD function supporting IEEE 802.3 (10Mb/s), 802.3u (100Mb/s),
802.3z and 802.3ab (1000Mb/s).
• Half- and full-duplex operation at 10/100.
• Full-duplex operation at 1000 Mbps.
• Up to 16 addresses for exact match unicast/multicast address filtering.
• Multicast address filtering based on 4,096-bit vectors in addition to promiscuous
unicast and promiscuous multicast filtering.
• MAC strips IEEE 802.1q VLAN tags and filters packets based on their VLAN ID. Up
to 4,096 VLAN tags are supported.
• Transmit path supports insertion of VLAN tag information on a packet-by-packet
basis.
• Flow control as defined in IEEE 802.3x as well as specific operation of asymmetrical
flow control defined by IEEE 802.3z and software controllable pause times and
threshold values.
• Programmable host memory receive buffers (256 Byte to 16 KByte) and cache line
size (16 to 256 Byte).
• 16 KByte configurable transmit and receive FIFO buffers with ECC protection.
• Wakeup.
• ACPI down functionality supporting D0 & D3 states.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1336
August 2009
Order Number: 320066-003US