EP80579 Datasheet, PDF (390/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-1. Bus 0, Device 0, Function 0: Summary of IMCH PCI Configuration Registers
(Sheet 2 of 2)
Offset Start Offset End
Register ID - Description
Default
Value
9Ch
9Dh
9Eh
9Fh
B8h
BCh
C4h
C6h
C8h
CAh
CCh
CEh
D8h
DEh
F6h
60h at 1h
70h at 4h
78h
64h
7Ch
84h
88h
8Ch
8Dh
90h
B0h
9Ch
9Dh
9Eh
9Fh
BBh
BFh
C5h
C7h
C9h
CBh
CDh
CFh
D8h
DFh
F6h
60h at 1h
73h at 4h
7Bh
67h
7Fh
87h
8Bh
8Ch
8Dh
93h
B3h
“Offset 9Ch: DEVPRES - Device Present Register” on page 408
33h
“Offset 9Dh: EXSMRC - Extended System Management RAM Control Register” on
page 409
00h
“Offset 9Eh: SMRAM - System Management RAM Control Register” on page 411 02h
“Offset 9Fh: EXSMRAMC - Expansion System Management RAM Control Register”
on page 413
07h
“Offset B8h: IMCH_MENCBASE: IA/ASU Shared Non-Coherent (AIOC-Direct)
Memory Base Address Register” on page 413
000FFFFFh
“Offset BCh: IMCH_MENCLIMIT - IA/ASU Shared Non-Coherent (AIOC-Direct)
Memory Limit Address Register” on page 414
00000000h
“Offset C4h: TOLM - Top of Low Memory Register” on page 415
0800h
“Offset C6h: REMAPBASE - Remap Base Address Register” on page 416
03FFh
“Offset C8h: REMAPLIMIT – Remap Limit Address Register” on page 416
0000h
“Offset CAh: REMAPOFFSET - Remap Offset Register” on page 417
0000h
“Offset CCh: TOM - Top Of Memory Register” on page 417
0000h
“Offset CEh: HECBASE - PCI Express Port A (PEA) Enhanced Configuration Base
Address Register” on page 418
E000h
“Offset D8h: CACHECTL0 - Write Cache Control 0 Register” on page 418
00h
“Offset DEh: SKPD - Scratchpad Data Register” on page 419
0000h
“Offset F6h: IMCH_TST2 - IMCH Test Byte 2 Register” on page 419
00h
“Offset 60h: DRB[0-3] - DRAM Row [3:0] Boundary Register” on page 421
ffh
“Offset 70h: DRA[0-1] - DRAM Row [0:1] Attribute Register” on page 422
00000515h
“Offset 78h: DRT0 - DRAM Timing Register 0” on page 424
242AD280h
“Offset 64h: DRT1 - DRAM timing Register 1” on page 431
12110000h
“Offset 7Ch: DRC - DRAM Controller Mode Register” on page 435
00000002h
“Offset 84h: ECCDIAG - ECC Detection/Correction Diagnostic Register” on
page 437
00000000h
“Offset 88h: SDRC - DDR SDRAM Secondary Control Register” on page 439
00000002h
“Offset 8Ch: CKDIS - CK/CK# Clock Disable Register” on page 441
00h
“Offset 8Dh: CKEDIS - CKE Clock Enable Register” on page 442
00h
“Offset 90h: SPARECTL - SPARE Control Register” on page 443
00000000h
“Offset B0h: DDR2ODTC - DDR2 ODT Control Register” on page 444
00000000h
Intel^® EP80579 Integrated Processor Product Line Datasheet
390
August 2009
Order Number: 320066-003US