EP80579 Datasheet, PDF (773/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
20.2.1.9 Offset 0Ah: DMA_WSM - DMA Write Single Mask Register
Table 20-12. Offset 0Ah: DMA_WSM - DMA Write Single Mask Register
Description:
View: IA F 1^a Base Address: 0000h (IO)
Offset Start: 0Ah
Offset End: 0Ah
View: IA F 1 Base Address: 0000h (IO)
Offset Start: 1Ah
Offset End: 1Ah
View: IA F 2^b Base Address: 0000h (IO)
Offset Start: D4h
Offset End: D4h
View: IA F 2 Base Address: 0000h (IO)
Offset Start: D5h
Offset End: D5h
Size: 8 bit
Default: 000001xxb
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
07 : 03
02
01 : 00
Reserved
CMS
DMACS
Reserved. Must be 0.
Channel Mask Select:
0 = DREQ is enabled for the selected channel
1 = DREQ is disabled for the selected channel
The channel is selected through bits [1:0]. Therefore, only
one channel can be masked / unmasked at a time.
DMA Channel Select: These bits select which DMA
Channel Mode Register is programmed.
00 Channel 0 (4) 01 Channel 1 (5)
10 Channel 2 (6) 11 Channel 3 (7)
a. View 1 describes the control registers for Channels 0-3.
b. View 2 describes the control registers for Channels 4-7.
Bit Reset
Value
00000b
1
XX
Bit Access
WO
WO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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