EP80579 Datasheet, PDF (1094/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
27.9.3 Read-Only Registers with Write Paths in ALT Access Mode
The registers described in Table 27-39 have write paths to them in ALT access mode.
Software will restore these values after returning from a powered down state. These
registers must be handled special by software. When in normal mode, writing to the
base address/count register also writes to the current address/count register.
Therefore, the base address/count must be written first, then the part is put into
alternate access mode and the current address/count register is written.
Only bits 3:0 of the DMA Status Registers listed below are writable.
Table 27-39. Register Write Accesses in Alternate Access Mode
I/O
Address
08h
D0h
Register Write Value
DMA Status Register for channels 0-3.
DMA Status Register for channels 4-7.
27.10 System Power Supplies, Planes, and Signals
27.10.1
Power Plane Control with SLP_S3#, SLP_S4# and SLP_S5#
The usage of SLP_S3# and SLP_S4# depend on whether the platform is configured for
S3-Cold.
• S3-Cold — The SLP_S3# output signal can be used to cut power to the system core
supply, since it will only go active for the STR state (typically mapped to ACPI S3).
Power must be maintained to system memory, CMI Resume Well, and to any other
circuits that need to generate Wake signals from the STR state.
Cutting power to the core may be done via the power supply, or by external FETs to the
motherboard.
The SLP_S4# and SLP_S5# output signal can be used to cut power to the system core
supply, as well as power to the system memory, since the context of the system is
saved on the disk. Cutting power to the memory may be done via the power supply, or
by external FETs to the motherboard. The SLP_S4# output signal is used to remove
power to additional subsystems that are powered during SLP_S3#.
SLP_S5# output signal can be used to cut power to the system core supply, as well as
power to the system memory, since the context of the system is saved on the disk.
Cutting power to the memory may be done via the power supply, or by external FETs to
the motherboard.
27.10.2
Note:
SLP_S4# and Suspend-To-RAM Sequencing
The system memory suspend voltage regulator is controlled by Glue logic. The
SLP_S4# signal must be used to remove power to system memory rather than
the SLP_S5# signal. The SLP_S4# logic in CMI provides a mechanism to fully
cycle the power to the DRAM and/or detect if the power is not cycled for a
minimum time.
To utilize the hardware-enforced minimum DRAM power-down feature that is
enabled by the SLP_S4# Assertion Stretch Enable bit (Section 27.3.1.3,
“Offset A4h: GEN_PMCON_3 - General PM Configuration 3 Register” bit 3), the
DRAM power must be controlled by the SLP_S4# signal.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1094
August 2009
Order Number: 320066-003US