EP80579 Datasheet, PDF (788/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
21.3.1.3
21.3.1.4
Bus Errors
If the first 8 bits specify an opcode which is not supported the slave will not respond
and wait for the next high to low transition on SPI_CS#.
SPI hardware should automatically discard 8-bit words that were not completely
received upon deassertion of the SPI_CS# signal.
Any other error correction or detection mechanisms must be implemented in firmware/
software.
Instructions
Instruction
Write Status
Data Program
Read Data
Write Disable
Read Status
Write Enable
Page Write
Fast Read⁽¹⁾
Ena Write Status
256B Erase
4KByte Erase
64KB Erase
Chip Erase
Auto Add Inc⁽²⁾
Power Down/Up
Read ID
ST
M25P80
(8 Mb)
01
02
03
04
05
06
-
0B
-
-
-
D8
C7
-
B9 / AB
-
ST
M45PE80
(8 Mb)
-
02
03
04
05
06
0A
0B
-
DB
-
D8
-
-
B9 / AB
9F
NexFlash
NX25P*
SST 25V040
(4Mb), SST
25VF080
(8 Mb)
01
01
02
02
03
03
04
04
05
05
06
06
-
-
0B
-
-
50
-
-
-
20
D8
52
C7
60
-
AF
B9
-
90
AB or 90
Ching is
(1 Mb)
01
02
03
04
05
06
-
0B
-
-
D7
D8
C7
-
-
AB
Notes:
1.
Fast Read Protocol is not supported
2.
The Auto Address Increment type is not supported.
Intel^® EP80579 Integrated Processor Product Line Datasheet
788
August 2009
Order Number: 320066-003US