EP80579 Datasheet, PDF (217/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
7.3.12 IA-32 Core Interface I/O-Mapped Register
Table 7-32. Summary of IA-32 Core Interface Registers Mapped in I/O Space
Offset Start Offset End
Register ID - Description
61h
70h
92h
F0h
CF9h
61h
70h
92h
F0h
CF9h
“Offset 61h: NMI_STS_CNT - NMI Status and Control Register” on page 1098
“Offset 70h: NMI_EN - NMI Enable (and Real Time Clock Index) Register” on
page 1099
“Offset 92h: PORT92 - Fast A20 and Init Register” on page 1100
“Offset F0h: COPROC_ERR - Coprocessor Error Register” on page 1100
“Offset CF9h: RST_CNT - Reset Control Register” on page 1101
Default
Value
00h
80h
00h
00h
00h
7.3.13
IMCH PCI Configuration
The PCI configuration interface includes the registers listed in Table 7-33. These
registers materialize at fixed locations in I/O space.
Table 7-33. Summary of IMCH PCI Configuration Registers Mapped in I/O Space
Offset Start Offset End
Register ID - Description
Default
Value
0CF8h
0CFCh
0CF8h
0CFCh
“Offset 0CF8h: CONFIG_ADDRESS: Configuration Address Register” on page 354 00000000h
“Offset 0CFCh: CONFIG_DATA: Configuration Data Register” on page 355
00000000h
7.3.14
APIC
The APIC includes the registers listed in Table 7-34 and Table 7-35 These registers
materialize at fixed locations in memory space and are indexed, respectively. See
Chapter 30.0 for detailed discussion of these registers.
Table 7-34. Summary of APIC Registers Mapped in Memory Space“
Offset Start Offset End
Register ID - Description
0000h (4B)
0010h (4B)
0040h (4B)
0000h (4B)
0010h (4B)
0040h (4B)
“APIC_IDX - Index Register” on page 1135
“APIC_DAT – Data Register” on page 1136
“APIC_EOI - EOI Register” on page 1136
Default
Value
00h
00h
00h
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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