EP80579 Datasheet, PDF (503/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.3.1.3 Offset 04h: PCICMD - PCI Command Register
Table 16-115.Offset 04h: PCICMD - PCI Command Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:1:0
Offset Start: 04h
Offset End: 05h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 : 11
10
09
08
07 : 02
01
00
Bit Acronym
Bit Description
Sticky
Reserved
INTxAD
FB2B
SERRE
Reserved
MAE
Reserved
Reserved
INTx Assertion DIsable: Controls the ability of a device
to generate INTx interrupt messages. This bit only applies
to legacy interrupts and not MSIs.
0 = Devices are permitted to generate INTx interrupt
messages.
1 = Devices are prevented from generating INTx interrupt
messages.
Fast Back-to-Back Enable: Not Applicable-hardwired to
0.
SERR Enable: This bit is a global enable bit for Device 1
SERR messaging. The DMA does not have an SERR#
signal. The DMA communicates the SERR condition by
sending an SERR message.
0 = Disable. SERR message is not generated for Device 1.
1 = Enable. Generate SERR messages for specific Device 1
error conditions that are individually enabled in the
EDMA_SERRCMD register. The error status is reported
in the EDMA_FERR, EDMA_NERR and PCISTS
registers.
Note: This bit only controls SERR messaging for Device
1. Devices 0 and 2–7 have their own SERR bits to
control error reporting for error conditions
occurring on their respective devices. The control
bits are used in a logical OR manner to enable the
SERR HI message mechanism
Reserved
Memory Access Enable:
0 = Device 1 memory space is disabled
Enable access to the EDMA Controller Low Base Address
Register
Reserved
Bit Reset
Value
00h
0b
0b
0b
00h
0b
0b
Bit Access
RW
RO
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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