EP80579 Datasheet, PDF (866/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
23.3.4
Port Interface Registers (One Set Per Port)
These registers implement various functions of the interface with an SATA device,
including the SATA superset registers of the SATA specification.
Table 23-63. Port Interface Registers for Ports[1:0]
Start
120
124
128
12C
130
134
138
13C
1A0
1A4
1A8
1AC
1B0
1B4
1B8
1BC
End
123
127
12B
12F
133
137
13B
13F
1A3
1A7
1AB
1AF
1B3
1B7
1BB
1BF
Symbol
P0TFD
P0SIG
P0SSTS
P0SCTL
P0SERR
P0SACT
P0CI
P0SNTF
P1TFD
P1SIG
P1SSTS
P1SCTL
P1SERR
P1SACT
P1CI
P1SNTF
Description
Port 0 Task File Data
Port 0 Signature
Port 0 Serial ATA Status
Port 0 Serial ATA Control
Port 0 Serial ATA Error
Port 0 Device Status
Port 0 Command Issue
Port 0 Serial ATA Notification
Port 1 Task File Data
Port 1 Signature
Port 1 Serial ATA Status
Port 1 Serial ATA Control
Port 1 Serial ATA Error
Port 1 Device Status
Port 1 Command Issue
Port 1 Serial ATA Notification
23.3.4.1
Offset 120h: PxTFD[0-1] – Port [0-1] Task File Data Register
This is a 32-bit register that copies specific fields of the task file when FISes are
received. The FISes that contain this information are:
• D2H Register FIS
• PIO Setup FIS
• Set Device Bits FIS (BSY and DRQ are not updated with this FIS)
Table 23-64. Offset 120h: PxTFD[0-1] – Port [0-1] Task File Data Register (Sheet 1 of 2)
Description:
View: PCI
BAR: ABAR
Bus:Device:Function: 0:31:2
Offset Start: 120h, 1A0h
Offset End: 123h, 1A3h
Size: 32 bit
Default: 0000007Fh
Power Well: Core
Bit Range
31 : 16
Bit Acronym
Reserved Reserved
Bit Description
Sticky
Bit Reset
Value
0h
Bit Access
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
866
August 2009
Order Number: 320066-003US