EP80579 Datasheet, PDF (761/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
1. I/O cycles and memory read cycles from the processor are not posted. Memory
write Cycles from the processor are posted.
2. DMA cycles can be pipelined. For example, after reading data from memory, the
LPC Controller can then release PHOLD# while it writes the data to the peripheral
on the LPC Interface. This is because there are no processor/SMI#-based retry
capabilities for DMA cycles. In the other direction, after reading data from a
peripheral, PHOLD# can be released while the DMA controller writes data to main
memory.
3. When bus masters read from main memory, the LPC Controller can treat this much
like DMA, and release the memory and PCI buses while the data is being
transferred to the bus master on the LPC Interface. When a bus master writes to
main memory, the LPC Controller can use the LPC Interface while the data is being
written to main memory.
19.3.11 Configuration
19.3.11.1 LPC Interface Decoders
To allow the I/O cycles and memory mapped cycles to go to the LPC interface, CMI
includes several decoders. During configuration, CMI must be programmed with the
same decode ranges as the peripheral. The decoders are programmed via the Device
31, Function 0 configuration space at offset 80h–87h.
Note:
CMI cannot accept PCI write cycles from PCI-to-PCI bridges or devices with similar
characteristics (specifically those with a “Retry Read” feature which is enabled) to an
LPC device if there is an outstanding LPC read cycle towards the same PCI device or
bridge. These cycles are not part of normal system operation, but may be encountered
as part of platform validation testing using custom test fixtures.
19.3.11.2 Bus Master Device Mapping and START Fields
Bus Masters must have a unique START field. In the case of the LPC Controller, which
supports two bus masters, it will drive 0010 for the START field for grants to bus
master 0 (requested via LDRQ[0]#) and 0011 for grants to bus master 1 (requested
via LDRQ[1]#.).
19.3.11.3 Firmware Memory IDSEL fields
The LPC Controller uses a unique IDSEL field for each EPROM. The IDSEL used is
determined through the programming of the FS1 and FS2 configuration registers.
19.3.12
SERR# Generation
Several internal and external sources of the LPC Bridge can cause SERR#, and are
described below.
The first class of errors is parity errors related internally to CMI. The LPC Bridge
captures generic data parity errors (errors it finds internally), as well as, errors
returned on internal cycles where the bridge was the master. If either of these two
conditions are met, and the bridge is enabled for parity error response, SERR# is
captured.
Additionally, if the bridge receives a target abort or master abort, and the bridge policy
is to SERR# on these types of aborts, SERR# is generated.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
761