EP80579 Datasheet, PDF (349/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
13.3
Note:
13.3.1
Note:
Routing Configuration Accesses
The IMCH supports up to two x4 PCI Express interfaces:
• PEA0
• PEA1
These two interfaces can be combined to form a x8 interface, PEA.
The IMCH is responsible for routing PCI configuration cycles to the proper interface. PCI
configuration cycles to IICH internal devices and downstream devices are routed to the
IICH via the internal NSI bus. PCI configuration cycles to the IMCH PCI Express
interfaces are routed to PEA(0:1). Routing of configuration accesses to PEA(0:1) is
controlled via the standard PCI-to-PCI bridge mechanism using information contained
within the PRIMARY BUS NUMBER, the SECONDARY BUS NUMBER, and the
SUBORDINATE BUS NUMBER registers of the corresponding PCI-to-PCI bridge device.
A detailed description of the mechanism for translating IA-32 core I/O bus cycles to
configuration cycles on one of the buses is described below.
The IMCH supports a variety of connectivity options. When any of the IMCH’s interfaces
are disabled, the associated interface’s device registers are hidden. All configuration
cycles (reads and writes) to disabled devices on bus #0 are forwarded to the NSI where
they will Master Abort.
Standard PCI Bus Configuration Mechanism
The PCI Bus defines a slot based “configuration space” that allows each device to
contain up to eight functions with each function containing up to 256 8-bit configuration
registers. The PCI Specification defines two bus cycles to access the PCI configuration
space: Configuration Read and Configuration Write. Memory and I/O spaces are
supported directly by the IA-32 core. Configuration space is supported by a mapping
mechanism implemented within the IMCH. The PCI Specification defines two
mechanisms to access configuration space, Mechanism #1 and Mechanism #2. CMI
supports Mechanism #1.
The configuration access mechanism makes use of the CONFIG_ADDRESS Register and
CONFIG_DATA Register. To reference a configuration register a Dword (32-bit) I/O write
cycle is used to place a value into CONFIG_ADDRESS that specifies the PCI bus, the
device on that bus, the function within the device, and a specific configuration register
of the device function being accessed. CONFIG_ADDRESS[31] must be a ‘1’ to enable a
configuration cycle. CONFIG_DATA then becomes a window into the four bytes of
configuration space specified by the contents of CONFIG_ADDRESS. Any read or write
to CONFIG_DATA will result in the IMCH translating the CONFIG_ADDRESS into the
appropriate configuration cycle.
The IMCH is responsible for translating and routing the IA-32 core I/O accesses to the
CONFIG_ADDRESS and CONFIG_DATA registers to internal IMCH configuration
registers, for NSI, and PCI Express ports PEA(0:1).
It is only possible to generate 1-4 byte configuration accesses via this mechanism,
which is in line with IMCH capabilities. The IMCH ONLY supports accesses up to 1
Dword (32 bits) in size into the configuration register space (internal or external).
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
349