EP80579 Datasheet, PDF (757/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 19-31. Offset F0h: RCBA: Root Complex Base Address Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:0
Offset Start: F0h
Offset End: F3h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 :14
13 :01
00
Bit Acronym
Bit Description
Sticky
BA
Reserved
EN
Base Address: Base Address for the root complex
register block decode range. This address is aligned on a
16 Kbyte boundary.
Reserved
Enable:
0 = Disables the range specified in BA to be claimed as
the RCRB (Root Complex Register Block)
1 = Enables the range specified in BA to be claimed as
the RCRB
Bit Reset
Value
0h
0h
0h
Bit Access
RW
RW
19.2.8
19.2.8.1
Manufacturing Information Register
Offset F8h: MANID: Manufacturer ID Register
Table 19-32. Offset F8h: MANID: Manufacturer ID Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:0
Offset Start: F8h
Offset End: FBh
Size: 32 bit
Default: 00010F90h
Power Well: Core
Bit Range
31 :24
23 :16
15 :08
07 :00
Bit Acronym
Bit Description
Sticky
Reserved
SID
MID
Reserved
Reserved
Stepping Identifier: This field increments for each
stepping of the part.
Note: This field can be used by software to differentiate
steppings when the Revision ID may not change.
Note: 00h for A0 stepping
Note: 01h for B0 stepping
A single Stepping ID can be implemented that is readable
from all functions in the chip because all of them
increment in lock-step.
Manufacturing Identifier: 0Fh = Intel
Reserved.
Bit Reset
Value
00h
01h
0Fh
90h
Bit Access
RO
RO
19.3
Interface
The LPC bridge function resides in Device 31, Function 0. In addition to the LPC bridge
function, D31, F0 contains other functional units including DMA, Interrupt controllers,
Timers, Power Management, System Management, GPIO, and RTC.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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