EP80579 Datasheet, PDF (897/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
24.2.1
Note:
24.2.1.1
SMBus Controller PCI Configuration Register Descriptions
For more information on the format of the register description tables that follow in this
chapter, see Section 7.1.1, “Register Description Tables” on page 183).
Offset 00h: VID: Vendor ID Register
Table 24-3. Offset 00h: VID: Vendor ID Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:3
Offset Start: 00h
Offset End: 01h
Size: 16 bit
Default: 8086h
Power Well: Resume
Bit Range Bit Acronym
Bit Description
15 : 00
VID
Vendor ID: This is a 16-bit value assigned to Intel
Sticky
Bit Reset
Value
8086h
Bit Access
RO
24.2.1.2 Offset 02h: DID: Device ID Register
Table 24-4. Offset 02h: DID: Device ID Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:3
Offset Start: 02h
Offset End: 03h
Size: 16 bit
Default: 5032h
Power Well: Resume
Bit Range
15 : 00
Bit Acronym
Bit Description
Sticky
DID
Device ID: Indicates the device number assigned by the
SIG.
Bit Reset
Value
5032h
Bit Access
RO
24.2.1.3 Offset 04h: CMD: Command Register
Table 24-5. Offset 04h: CMD: Command Register (Sheet 1 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:3
Offset Start: 04h
Offset End: 05h
Size: 16 bit
Default: 0000h
Power Well: Resume
Bit Range Bit Acronym
Bit Description
15 : 11
10
09
Reserved
INTD
FBE
Reserved
Interrupt Disable:
0 = Enable (default)
1 = Disables SMBus to assert its PIRQB# signal
Fast Back to Back Enable: Reserved as ‘0’.
Sticky
Bit Reset
Value
0h
Bit Access
0b
RW
0b
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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