EP80579 Datasheet, PDF (1235/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
5. Revision: This is the 1st version of this device, so the revision number is 0x00.
6. Class Code: The class code, 0x020000 identifies this device as an Ethernet
adapter.
7. Cache Line Size: Used to store the cache line size. The value is in units of 4 bytes.
A system with a cache line size of 64B sets the value of this register to 0x10. The
only sizes that are supported are 16, 32, 64, and 128 bytes. All other sizes are
treated as 0. See exceptions in section 2.11.8 The default value at power up in
0x00.
8. Unsupported values affect PCI cache line support. All writes default to using the
memory write (MW) command, and memory read command determination uses a
cache-line size of 32 bytes.
9. Latency Timer: The lower 2 bits are not implemented and return 0. The upper 6
bits are RW. The default value of the Latency Timer register is 64 in PCI-X mode.
10. Header Type: This indicates if a device is single function or multifunction. The
EP80579 returns a value of 0x00, indicating that it is a normal single function
device.
11. BIST: BIT (Built in Self-test) will be not be implemented as supportable from PCI
config space in this version of the device.
12. Base Address Register: The Base Address Registers (or BARs) are used to map the
EP80579 register space to system memory space.
35.4
Interrupt Handling for AIOC Devices
Interrupts from the AIOC devices are routed towards the IA-32 core as either an MSI or
by asserting the level-sensitive signal INTx.
The configuration provides a mechanism via the PCI configuration header space for
functional units in the AIOC to interrupt the IA-32 core.
Most PCI configuration headers for AIOC devices implement two capability records to
support interrupt and signal handling.
• A Message Signalled Interrupt capability record that follows the standard PCI
format and describes the format of an IA MSI.
• An EP80579-specific Signal Target capability record that is unique to the EP80579
and describes how to target signals from the device.
The hardware will provide these capabilities to most of the devices implemented in the
Configuration Bridge except for MDIO and the Local Expansion Bus. The software is
responsible to enabling/disabling this functionality for each of the devices.
Table 35-2. Messaging and Signalling Capability Record per PCI Device (Sheet 1 of 2)
PCI
Device
0
(GbE0)
1
(GbE 1)
2
(GbE 2)
Function
GbE
GbE
GbE
Message
Capable?
Yes
Yes
Yes
Signal
Capable?
Interrupts
(Max 8 per device)
GBE0 Interrupt 0
Yes
GBE0 Interrupt 1
GBE0 Error Interrupt
GBE1 Interrupt 0
Yes
GBE1 Interrupt 1
GBE1 Error Interrupt
GBE2 Interrupt 0
Yes
GBE2 Interrupt 1
GBE2 Error Interrupt
Comment
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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