EP80579 Datasheet, PDF (481/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.2.1.34 Offset E4h: NSIERRINJCTL - NSI Error Injection Control Register
This register controls the way in which the IMCH handles parity errors on the Interface.
Table 16-88. Offset E4h: NSIERRINJCTL - NSI Error Injection Control Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:1
Offset Start: E4h
Offset End: E7h
Size: 32 bit
Default: 00040000h
Power Well: Core
Bit Range
31 : 20
19
18
17 : 00
Bit Acronym
Bit Description
Sticky
Reserved
STPSCRM
EnDP
Reserved
Reserved
Stop and Scream bit: This is a special control for errors
going to NSI, outgoing from the IMCH core.
0 = Outgoing data errors are propagated.
1 = Outgoing data errors are reported, but not propagated.
Enable data poisoning: This bit controls whether or not
the IMCH marks data as “poisoned” when a parity error is
detected from the NSI.
0 = Error checking disabled.
1 = Error Checking Enabled. Incoming data with parity
errors are marked as “poisoned” before being sent on
towards its destination.
Reserved
Bit Reset
Value
00h
0b
1b
0b
Bit Access
RW
RW
16.2.1.35 Offset E8h: BERRINJCTL - Buffer Error Injection Control Register
This register enables the injection of errors on data read out of the posted write buffer.
The lower 16 bits are the corresponding flip parity bits for the cacheline of data. The
upper bits in the register are for the use and control of the associated flip parity bits.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
481