EP80579 Datasheet, PDF (1649/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
41.6.1.9 Offset 0020h: TS_SysTimeLo - System Time Low Register
Register
Name
TS_SysTimeLo
Access
(See below.) Reset Value 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SystemTime_Low[31:0]
Table 41-19. Offset 0020h: TS_SysTimeLo Register
Description:
View: PCI
BAR: CSRBAR
Bus:Device:Function: M:7:0
Offset Start: 00000020h
Offset End: 00000023h
Size: 32 bits
Default: 0000h
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
31 : 0
The system timer is a loadable up-counter, and reflects
the local time in the module. While the system timer is 64
bits wide, the lower 32 bits reside in this register. The
system timer is clocked by the module system clock and
incremented when the Accumulator register rolls over.
To read the entire system time value, the user must read
this location first. Reading this location captures the upper
32 bits of the system time in a temporary register, which
SystemTime_Lo is accessed when the user reads the SystemTime_High
w
Register next.
Likewise, the SystemTime_Low Register must be written
first when the user wants to write a new 64-bit value to
system time. The data written to this register is captured
in a holding register. When the user writes to the
SystemTime_High Register, all 64 bits are then written to
the system timer. Updating the system time with a direct
write has precedence over increments to the system time
based on an Accumulator rollover.
Bit Reset
Value
0000h
Bit Access
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1649