EP80579 Datasheet, PDF (1532/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.6.50 MPTC – Multicast Packets Transmitted Count Register
This register counts the number of multicast packets transmitted. This register does
not include flow control packets and increments only if transmits are enabled.
Table 37-127.MPTC: Multicast Packets Transmitted Count Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 40F0h
Offset End: 40F3h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 40F0h
Offset End: 40F3h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 40F0h
Offset End: 40F3h
Size: 32 bits
Default: 00000000h
Power
Well:
GbE0: Aux
Gbe1/2: Core
Bit Range Bit Acronym
Bit Description
31 : 00
MPTC
Number of multicast packets transmitted
Sticky
Bit Reset
Value
0h
Bit Access
RC
37.6.6.51 BPTC – Broadcast Packets Transmitted Count Register
This register counts the number of broadcast packets transmitted. This register will
only increment if transmits are enabled.
Table 37-128.BPTC: Broadcast Packets Transmitted Count Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 40F4h
Offset End: 40F7h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 40F4h
Offset End: 40F7h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 40F4h
Offset End: 40F7h
Size: 32 bits
Default: 00000000h
Power
Well:
GbE0: Aux
Gbe1/2: Core
Bit Range Bit Acronym
Bit Description
31 : 00
BPTC
Number of broadcast packets transmitted count
Sticky
Bit Reset
Value
0h
Bit Access
RC
Intel^® EP80579 Integrated Processor Product Line Datasheet
1532
August 2009
Order Number: 320066-003US