EP80579 Datasheet, PDF (864/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 23-62. Offset 118h: PxCMD[0-1] – Port [0-1] Command Register (Sheet 2 of 3)
Description:
View: PCI
BAR: ABAR
Bus:Device:Function: 0:31:2
Offset Start: 118h, 198h
Offset End: 11Bh, 19Bh
Size: 32 bit
Default: Variable
Power Well: Core
Bit Range
24
23 :22
21
20
19
18
17
16
15
14
13
Bit Acronym
Bit Description
Sticky
Bit Reset
Value
ATAPI
Reserved
ESP
CPD
ISP
HPCP
Reserved
Reserved
CR
FR
ISS
Device is ATAPI (ATAPI): When set, the connected
device is an ATAPI device. This bit is used by the HBA to
control whether or not to generate the desktop LED when
commands are active.
Reserved
External SATA Port (ESP): when set to '1', indicates that this
port is routed externally and will be used with an external
SATA device. When set to '1' HCAP.SXS must also be set to
'1'. When cleared ('0'), indicates that this port is not routed
externally and supports internal SATA devices only. ESP is
mutually exclusive with the HPCP bit in this register
Cold Presence Detection (CPD): The SATA controller
does not support cold presence detect.
Interlock Switch Attached to Port (ISP): When
interlock switches are supported in the platform (HCAP.SIS
set), this indicates whether this particular port has an
interlock switch attached. This bit can be used by system
software to enable such features as aggressive power
management, as disconnects can always be detected
regardless of PHY state with an interlock switch. When this
bit is set, it is expected that HPCP in this register is also set.
The HBA takes no action on the state of this bit – it is for
system software only. For example, if this bit is cleared, and
an interlock switch toggles, the HBA shall still treat it as a
proper interlock switch event.
Note that this bit is not reset on a HBA reset.
Hot Plug Capable Port (HPCP): This indicates whether
the this port is connected to a device which can be hot
plugged. SATA by definition is hot-pluggable, but not all
platforms are constructed to allow the device to be removed
(it may be screwed into the chassis, for example). This bit
can be used by system software to indicate a feature such
as “eject device” to the end-user.
The HBA takes no action on the state of this bit – it is for
system software only. For example, if this bit is cleared, and
a hot plug event occurs, the HBA shall still treat it as a
proper hot plug event.
Note that this bit is not reset on a HBA reset.
Reserved.
Reserved
Command List Running (CR): When this bit is set it
indicates that the command list DMA engine for the port is
running.
FIS Receive Running (FR): When this bit is set it
indicates that the FIS Receive DMA engine for the port is
running.
Interlock Switch State (ISS): For HBAs that support
interlock switches (HCAP.SIS=1), this bit indicates the
current state of the interlock switch. A ‘0’ indicates the
switch is closed, and a ‘1’ indicates the switch is opened.
For HBAs that do not support interlock switches
(HCAP.SIS=0), this bit reports ‘0’.
Software should only use this bit if both HCAP.SIS and
PxCMD.ISP are set to ‘1’.
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
Variable
Bit Access
RW
RO
RWO
RO
RWO
RWO
RO
RO
RO
RO
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
864
August 2009
Order Number: 320066-003US