EP80579 Datasheet, PDF (57/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

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Bus 0, Device 1, Function 0: Summary of EDMA Configuration Registers Mapped Through
EDMALBAR Memory BAR ................................................................................... 197
Bus 0, Device 2, Function 0: Summary of PCI Express Port A Standard and Enhanced PCI
Configuration Registers ..................................................................................... 200
Bus 0, Device 3, Function 0: Summary of PCI Express Port A1 Standard and Enhanced PCI
Configuration Registers ..................................................................................... 203
Bus 0, Device 29, Functions 0, Summary of USB (1.1) Controller PCI Configuration
Registers ........................................................................................................ 206
Summary of USB (1.1) Controller Configuration Registers Mapped Through USBIOBAR
I/O BAR .......................................................................................................... 206
Bus 0, Device 29, Function 7: Summary of USB (2.0) Controller PCI Configuration
Registers ........................................................................................................ 207
Bus 0, Device 29, Function 7: Summary of USB (2.0) Controller Configuration Registers
Mapped Through MBAR Memory BAR .................................................................. 208
Bus 0, Device 31, Function 0: Summary of Root Complex Configuration Registers Mapped
Through RCBA Memory BAR............................................................................... 209
Bus 0, Device 31, Function 0: Summary of LPC Interface PCI Configuration Registers 210
Bus 0, Device 31, Function 0: Summary of LPC Interface Power Management PCI
Configuration Registers ..................................................................................... 211
Bus 0, Device 31, Function 0: Summary of TCO Configuration Registers Mapped Through
TCOBASE I/O BAR“........................................................................................... 211
Bus 0, Device 31, Function 0: Summary of LPC Interface Power Management General
Configuration Registers Mapped Through PMBASE I/O BAR .................................... 211
Bus 0, Device 31, Function 0: Summary of General Purpose I/O Configuration Registers
Mapped Through GBA BAR IO BAR...................................................................... 212
Bus 0, Device 31, Function 2: Summary of SATA Controller PCI Configuration
Registers ........................................................................................................ 213
Bus 0, Device 31, Function 2: Summary of SATA Controller Configuration Registers
Mapped Through LBAR I/O BAR.......................................................................... 214
Bus 0, Device 31, Function 2: Summary of SATA Controller Configuration Registers
Mapped Through ABAR Memory BAR ................................................................... 214
Bus 0, Device 31, Function 3: Summary of SMBus Controller PCI Configuration
Registers ........................................................................................................ 216
Bus 0, Device 31, Function 3: Summary of SMBus Controller Configuration Registers
Mapped Through SM_BASE I/O BAR.................................................................... 216
Summary of IA-32 Core Interface Registers Mapped in I/O Space ........................... 217
Summary of IMCH PCI Configuration Registers Mapped in I/O Space ....................... 217
Summary of APIC Registers Mapped in Memory Space“ ......................................... 217
Summary of APIC Indexed Registers................................................................... 218
Summary of 8259 Interrupt Controller (PIC) Registers Mapped in I/O Space ............ 219
Summary of APM Registers Mapped in I/O Space.................................................. 219
Summary of LPC DMA Registers Mapped in I/O Space ........................................... 220
0000h (IO) Base Address Registers in the IA F1 View ............................................ 220
0000h (IO) Base Address Registers in the IA F2 View ............................................ 221
Summary of 8254 Timer Registers Mapped in I/O Space........................................ 221
Summary of HPET Registers Mapped in Memory Space .......................................... 222
Summary of UART Timer registers in I/O space .................................................... 222
Summary of Watchdog Timer Registers in I/O Space............................................. 223
Summary of Real Time Clock Indexed Registers ................................................... 223
Bus 0, Device 4, Function 0: Summary of PCI-to-PCI Bridge PCI Configuration
Registers ........................................................................................................ 224
Bus M, Device 0, Function 0: Summary of Gigabit Ethernet MAC Interface PCI
Configuration Registers ..................................................................................... 226
Bus M, Device 1, Function 0: Summary of Gigabit Ethernet MAC Interface PCI
Configuration Registers ..................................................................................... 227
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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