EP80579 Datasheet, PDF (737/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 19-5. Offset 08h: RID: Revision ID Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:0
Offset Start: 08h
Offset End: 08h
Size: 8 bit
Default: Variable
Power Well: Core
Bit Range
07 :00
Bit Acronym
Bit Description
RID
Revision ID: Indicates the part revision
Sticky
Bit Reset
Value
Variable
Bit Access
RWO
19.2.1.5 Offset 09h: CC: Class Code Register
Table 19-6. Offset 09h: CC: Class Code Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:0
Offset Start: 09h
Offset End: 0Bh
Size: 24 bit
Default: 060100h
Power Well: Core
Bit Range
23 :16
15 :08
07 :00
Bit Acronym
Bit Description
Sticky
BCC
SCC
PI
Base Class Code: indicates the type of device for the LPC
bridge.
06h = Bridge device.
Sub-Class Code: Indicates the category of bridge for the
LPC bridge.
01h = PCI-to-ISA bridge.
Programming Interface: The LPC bridge has no
programming interface.
Bit Reset
Value
06h
01h
00h
Bit Access
RO
RO
RO
19.2.1.6 Offset 0Dh: MLT: Master Latency Timer Register
Table 19-7. Offset 0Dh: MLT: Master Latency Timer Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:0
Offset Start: 0Dh
Offset End: 0Dh
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 :03
02 :00
Bit Acronym
Bit Description
MLC
Reserved
Master Latency Count: Reserved per PCI Express
Specification.
Reserved
Sticky
Bit Reset
Value
Bit Access
0h
RO
0h
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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