EP80579 Datasheet, PDF (1594/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 39-12. Offset 00000020h: TxMessageControl[0-7] - Transmit Message Control and
Command (Sheet 2 of 2)
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:4:0
00000020h
Offset Start: at 10h
Offset End: 00000023h
at 10h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:5:0
00000020h
Offset Start: at 10h
Offset End: 00000023h
at 10h
Size: 32 bit
Default: XXXXXXXXh
Power Well: Core
Bit Range
02
01
00
Bit Acronym
Bit Description
Sticky
TxIntEbl
TxAbort
TxReq
Tx Interrupt Enable
‘0’: Interrupt disabled.
‘1’: Interrupt enabled, successful message transmission
set the TxMsg flag in the interrupt controller.
Transmit Abort Request
‘0’: Idle
‘1’: Requests removal of a pending message. The message
is removed the next time an arbitration loss happened.
The flag is cleared when the message was removed or
when the message won arbitration. The TxReq flag is
released at the same time.
Transmit Request
Write:
‘0’: Idle.
‘1’: Message Transmit Request. The Tx message buffer
must not be changed while TxReq is ‘1’.
Read:
‘0’: TxReq completed.
‘1’: TxReq pending.
Bit Reset
Value
Xh
Xh
Xh
Bit Access
RW
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1594
August 2009
Order Number: 320066-003US